WS7: VMX/VSX Implementation

Owner: TBD Duration: 24-32 weeks Priority: High (Critical for LCS Compliance)

💬 Discuss WS7: This is our most complex workstream! Join #powercommons:matrix.org to discuss VMX/VSX implementation strategies, share resources, or collaborate on this critical component.

Objectives

Implement VMX (AltiVec) and VSX (Vector-Scalar Extension) for Linux Compatible Subset (LCS) compliance.

Critical Importance

This is the largest and most resource-intensive workstream. Without VMX/VSX:

• ❌ Cannot run standard Linux distributions (Fedora, Ubuntu, RHEL)
• ❌ glibc requires VMX/VSX for optimized string and memory operations
• ❌ Many applications fail (compiled with -mcpu=power8 or later)
• ❌ Only achieves SFFS (Server Floating Point Subset), not LCS

With VMX/VSX:

• ✅ LCS Compliance - industry standard for Linux on POWER
• ✅ Run unmodified distros - Fedora, Ubuntu, RHEL work out-of-box
• ✅ Application compatibility - vast majority of ppc64le software works
• ✅ Performance - SIMD operations for HPC, multimedia, crypto

Background

VMX (Vector Multimedia Extension)

Also known as AltiVec, VMX provides:

• 32 x 128-bit vector registers (VR0-VR31)
• SIMD operations on integer and floating-point data
• Data types: byte, halfword, word, single-precision float
• ~200 instructions for parallel processing
• Introduced in POWER6, based on original AltiVec

VSX (Vector-Scalar Extension)

VSX extends VMX with:

• 64 x 128-bit registers (VSR0-VSR63)
  • VSR0-VSR31 overlay FPR0-FPR31 (scalar FP registers)
  • VSR32-VSR63 overlay VR0-VR31 (VMX vector registers)
• Double-precision floating-point SIMD
• Scalar and vector operations in unified register file
• ~200 additional instructions
• Introduced in POWER7

Register File Organization

VSX View (64 x 128-bit registers):
┌─────────────────────────────────────────┐
│ VSR0-31  (overlay FPR0-31 in low 64b)  │ ← Scalar FP + VSX
│ VSR32-63 (overlay VR0-31)              │ ← VMX vectors
└─────────────────────────────────────────┘

Legacy View:
FPR0-31:  64-bit scalar floating-point (existing A2 registers)
VR0-31:   128-bit VMX vector registers (NEW)

Tasks

Phase 0: Planning and Architecture (Weeks 1-2)

Phase 1: Register File and Basic Infrastructure (Weeks 3-6)

Phase 2: VMX Integer Instructions (Weeks 7-12)

VMX Integer Arithmetic

VMX Integer Logic and Shift

VMX Integer Compare and Permute

Phase 3: VMX Floating-Point Instructions (Weeks 13-16)

Issues #262-283: VMX Single-Precision FP (22 instructions)

• Priority: High
• Duration: 15 days total
• Categories: Arithmetic, Compare, Convert, Rounding, Estimate

Key Instructions:

• Vector FP add/subtract: vaddfp, vsubfp
• Vector FP multiply-add: vmaddfp
• Vector FP compare: vcmpeqfp, vcmpgtfp, vcmpgefp, vcmpbfp
• Vector FP convert: vcfsx, vcfux, vctsx, vctux
• Vector FP rounding: vrfin, vrfiz, vrfip, vrfim
• Vector FP estimate: vrefp, vrsqrtefp, vlogefp, vexptefp
• Vector FP min/max: vmaxfp, vminfp

Implementation Notes:

• Reuse existing FPU if possible
• May need 4-way SIMD FPU (expensive)
• Consider multi-cycle execution
• Ensure IEEE 754 compliance
• Labels: phase:3-vmx-fp, category:fp-ops, precision:single

Phase 4: VMX Load/Store Instructions (Weeks 17-18)

Issues #284-315: VMX Memory Operations (32 instructions)

• Priority: High
• Duration: 10 days total
• Categories: Load, Store, Pack, Unpack

Key Instructions:

• Vector load: lvx, lvxl (aligned)
• Vector store: stvx, stvxl (aligned)
• Vector load element: lvebx, lvehx, lvewx
• Vector store element: stvebx, stvehx, stvewx
• Vector load splat: lvsplatb, lvsplath, lvsplatw
• Vector alignment: lvsl, lvsr (load vector for shift left/right)
• Pack/unpack: vpkuhum, vpkuwum, vpkuhus, vpkuwus, vpkshss, vpkswss, vpkshus, vpkswus, vpkpx, vupkhsb, vupkhsh, vupklsb, vupklsh, vupkhpx, vupklpx

Implementation Notes:

• Most VMX loads/stores require 16-byte alignment
• Unaligned access requires multiple operations + permute
• Trap on misalignment or emulate in software
• Pack/unpack operations convert between widths with saturation
• Labels: phase:4-vmx-load-store, category:memory, category:pack-unpack

Phase 5: VSX Scalar Instructions (Weeks 19-22)

Issues #316-367: VSX Scalar Double-Precision (52 instructions)

• Priority: High
• Duration: 20 days total
• Categories: Arithmetic, Compare, Convert, Estimate, Special

Key Instructions:

• Scalar FP add/subtract: xsadddp, xssubdp
• Scalar FP multiply/divide: xsmuldp, xsdivdp
• Scalar FP multiply-add: xsmaddadp, xsmaddmdp, xsmsubadp, xsmsubmdp, xsnmaddadp, xsnmaddmdp, xsnmsubadp, xsnmsubmdp
• Scalar FP compare: xscmpudp, xscmpodp, xscmpeqdp, xscmpgtdp, xscmpgedp
• Scalar FP convert: xscvdpsp, xscvspdp, xscvdpsxds, xscvdpsxws, xscvdpuxds, xscvdpuxws, xscvsxddp, xscvuxddp, xscvsxdsp, xscvuxdsp
• Scalar FP sqrt: xssqrtdp
• Scalar FP reciprocal estimate: xsredp, xsrsqrtedp
• Scalar FP abs/negate/copy sign: xsabsdp, xsnabsdp, xsnegdp, xscpsgndp
• Scalar FP max/min: xsmaxdp, xsmindp
• Scalar FP round/truncate: xsrdpic, xsrdpim, xsrdpip, xsrdpiz, xsrdpi

Implementation Notes:

• VSX scalar ops use VSR0-63 (overlap with FPR0-31)
• Higher precision than VMX single-precision
• IEEE 754 compliance required
• Labels: phase:5-vsx-scalar, category:fp-ops, precision:double

Phase 6: VSX Vector Instructions (Weeks 23-26)

Issues #368-456: VSX Vector Instructions (89 instructions)

• Priority: High
• Duration: 48 days total
• Categories: FP Arithmetic, FP Compare, FP Convert, Logical, Permute, Load/Store

VSX Vector FP Arithmetic (Double/Single Precision):

• Vector FP add/subtract: xvadddp, xvaddsp, xvsubdp, xvsubsp
• Vector FP multiply/divide: xvmuldp, xvmulsp, xvdivdp, xvdivsp
• Vector FP multiply-add: xvmaddadp, xvmaddmdp, xvmsubadp, xvmsubmdp, xvnmaddadp, xvnmaddmdp, xvnmsubadp, xvnmsubmdp (both DP and SP variants)
• Vector FP sqrt: xvsqrtdp, xvsqrtsp
• Vector FP reciprocal estimate: xvredp, xvresp, xvrsqrtedp, xvrsqrtesp
• Vector FP max/min: xvmaxdp, xvmaxsp, xvmindp, xvminsp

VSX Vector FP Compare & Convert:

• Vector FP compare: xvcmpeqdp, xvcmpeqsp, xvcmpgtdp, xvcmpgtsp, xvcmpgedp, xvcmpgesp
• Vector FP convert: xvcvdpsp, xvcvspdp, xvcvdpsxds, xvcvdpsxws, xvcvdpuxds, xvcvdpuxws, xvcvspsxds, xvcvspsxws, xvcvspuxds, xvcvspuxws, xvcvsxddp, xvcvsxdsp, xvcvsxwdp, xvcvsxwsp, xvcvuxddp, xvcvuxdsp, xvcvuxwdp, xvcvuxwsp
• Vector FP round/truncate: xvrdpic, xvrdpim, xvrdpip, xvrdpiz, xvrdpi, xvrspic, xvrspim, xvrspip, xvrspiz, xvrspi
• Vector FP abs/negate/copy sign: xvabsdp, xvabssp, xvnabsdp, xvnabssp, xvnegdp, xvnegsp, xvcpsgndp, xvcpsgnsp

VSX Permute & Logical Operations:

• Permute: xxpermdi, xxsldwi
• Select: xxsel
• Merge: xxmrghw, xxmrglw
• Splat: xxspltw
• Logical: xxland, xxlandc, xxlor, xxlorc, xxlxor, xxlnor, xxleqv, xxlnand

VSX Load/Store Operations:

• Load/store doubleword: lxsdx, stxsdx
• Load/store word: lxsiwax, lxsiwzx, stxsiwx
• Load/store vector: lxvd2x, lxvw4x, stxvd2x, stxvw4x, lxvdsx

Implementation Notes:

• VSX vector operations process 2x double-precision or 4x single-precision values in parallel
• Uses VSR0-63 (full 128-bit registers)
• Requires careful SIMD execution unit design
• Labels: phase:6-vsx-vector, category:fp-ops, category:logical, category:permute, category:memory

Phase 7: Exception and Context Management (Weeks 27-28)

Issues #457-460: Exception and Context Management (4 issues)

• Priority: Critical
• Duration: 32 days total
• Categories: Exception handling, Context switching, Register coherency

Phase 8: Testing and Verification (Weeks 29-32)

Issues #461-464: Testing and Verification (4 issues)

• Priority: Critical
• Duration: 60 days total
• Categories: Unit testing, Integration testing, Performance testing

Instruction Count Summary

Note: Actual count varies by ISA version, some instructions optional.

Integration with A2 Core

Pipeline Integration

┌─────────┐   ┌────────┐   ┌─────────┐   ┌────────┐   ┌──────────┐
│ I-Fetch │ → │ Decode │ → │ Issue   │ → │ VMX/   │ → │ Write-   │
│         │   │        │   │         │   │ VSX    │   │ back     │
│         │   │        │   │         │   │ EXU    │   │          │
└─────────┘   └────────┘   └─────────┘   └────────┘   └──────────┘
                                              ↓
                                         VR0-31, VSR0-63
                                         Register File

Key Integration Points

1. Instruction Decode: Recognize VMX/VSX opcodes
2. Issue Logic: Schedule to VMX/VSX execution unit
3. Register Renaming: Extend to vector registers (if applicable)
4. Execution: New 128-bit datapath
5. Writeback: Write 128-bit results to register file
6. Load/Store Unit: Handle 16-byte vector operations
7. Exception Logic: VMX/VSX unavailable exceptions

Potential Issues

• Frequency Impact: 128-bit datapath may slow critical path
• Area: Large register file (64 x 128-bit = 8KB)
• Power: Vector operations consume more power
• Verification: 400+ new instructions to verify

Dependencies

• WS1: Some VMX/VSX instructions depend on base ISA updates
• Parallel with WS2, WS3, WS4
• Must complete before WS9 (integration)

Success Criteria

• All mandatory LCS VMX/VSX instructions implemented
• Register file (64 x 128-bit) functional
• Exception handling (unavailable exception) works
• Context switching validated
• Pass ISA compliance VMX/VSX tests
• glibc test suite passes (critical for LCS)
• Linux boots with VMX/VSX enabled
• Standard Linux distributions (Fedora, Ubuntu) boot

Critical Risks

Risk 1: Schedule Overrun

Probability: High Impact: Critical Mitigation:

• Evaluate open source options early
• Consider phased approach (VMX first)
• Allocate contingency time

Risk 2: Frequency Degradation

Probability: Medium Impact: High Mitigation:

• Multi-cycle execution for complex operations
• Pipeline vector operations
• Careful physical design

Risk 3: Verification Complexity

Probability: High Impact: High Mitigation:

• Start verification early
• Reuse ISA compliance tests
• Automated test generation

Deliverables

1. ✅ VMX/VSX architecture specification
2. ✅ RTL implementation (all instructions)
3. ✅ 64 x 128-bit register file
4. ✅ Exception handling
5. ✅ Test suite (unit and integration tests)
6. ✅ Verification report (compliance test results)
7. ✅ Integration guide
8. ✅ Performance benchmarks

Timeline Visualization

Week   Phase                          Key Deliverable
----   -----                          ---------------
1-2    Planning                       ✓ Architecture spec
3-6    Register file                  ✓ VR0-31, VSR0-63
7-12   VMX integer                    ✓ ~75 instructions
13-16  VMX floating-point            ✓ ~50 instructions
17-18  VMX load/store                ✓ ~25 instructions
19-22  VSX scalar                     ✓ ~50 instructions
23-26  VSX vector                     ✓ ~100 instructions
27-28  Exception handling             ✓ Context switching
29-32  Testing & integration          ✓ LCS compliance

Risk Windows:
Week 3-6:   High (register file area and timing)
Week 13-16: High (floating-point implementation complexity)
Week 29-32: Medium (verification and debugging)

References

• Power ISA v3.1C Book I, Chapters 6 & 7
• AltiVec Programming Interface Manual
• VSX Programming Guide
• glibc source: sysdeps/powerpc/powerpc64/
• Linux kernel: arch/powerpc/kernel/vector.S
• OpenPOWER Foundation: VMX/VSX compliance tests

Status: Planning Next Step: Requirements analysis and open source evaluation (Issue #170)

Issues

Status: 295 open, 0 closed (0/295 complete)

Last updated: 2025-12-05 16:48:17