PowerCommons - The Open Silicon Commons

Welcome to PowerCommons

PowerCommons is an ambitious initiative to create the world’s first fully open, verifiable, and sovereign computing infrastructure based on the OpenPower architecture. We’re reviving and modernizing proven processor designs to deliver transparent, auditable, and secure computing platforms that serve the public interest rather than corporate surveillance.

In an era where digital infrastructure determines economic and political power, PowerCommons represents a crucial step toward technological independence and democratic control over computing resources.

🎯 Our Mission

To democratize access to high-performance, secure, and transparent computing by creating fully open-source processor implementations and system architectures that can be verified, modified, and deployed by anyone, anywhere, without proprietary dependencies or hidden backdoors.

📊 Project Status Summary

🚀 Current Projects

PowerPC Support in LiteX SoC Framework: A Microwatt Linux Implementation on VCU-118

Added PowerPC support to the LiteX framework addressing boot and BIOS issues for PowerPC boot sequences and device tree generation conflicts to achieve full Linux boot on VCU-118 hardware.

Status: Active Development | Learn More →

From OpenPower to PowerCommons: Resurrecting and Modernizing the A2O Core

Breathing new life into IBM’s battle-tested A2O processor - the powerhouse behind Blue Gene/Q supercomputers - making it accessible on modern FPGA platforms.

Status: Active Development | Learn More →

PowerCommons SoC Platform

Creating the world’s first completely open System-on-Chip with verifiable security from boot to application, eliminating all proprietary components including the BMC.

Status: Architecture Phase | Learn More →

🚀 Completed Projects

Adding VCU-118 board support to Microwatt SoC

Expanded Microwatt SoC’s hardware compatibility by implementing full VCU-118 board support, including platform-specific LiteDRAM controller adaptation with custom pin configurations and clock settings. Status: Completed | Learn More →

🏛️ Why This Matters

Digital Sovereignty

Every major processor today contains hidden management engines, proprietary firmware, and unauditable code paths. PowerCommons changes this paradigm by ensuring every transistor’s behavior can be inspected and verified.

Post-Surveillance Computing

In alignment with post-capitalist visions of technology, PowerCommons creates computing infrastructure that serves communities rather than extracting value from them.

Technological Commons

Like public utilities and infrastructure, fundamental computing technology should be a commons - collectively owned, transparently operated, and democratically governed.

🤝 Join the Movement

For Developers

• 📦 Code Repository: codeberg.org/PowerCommons
• 🔧 Get Started: Coming soon!
• 💬 Matrix Chat: coming soon!

For Organizations

• 🏛️ Government & Critical Infrastructure: Deploy verifiable, sovereign computing
• 🎓 Academic Institutions: Research and teach with fully transparent systems
• 🏢 Industry Partners: Build secure products on open foundations

For Citizens

• 📖 Learn: Understand why open hardware matters for democracy
• 🗣️ Advocate: Support policies promoting open infrastructure
• 💰 Support: Contribute to sustainable development

🌍 Ecosystem Partners

📰 Latest Updates

September 2025: NLnet Funding Proposals Submitted

Two comprehensive proposals totaling €100,000 submitted for A2O revival and SoC development…

August 2025: MicroWatt VCU118 Success

Successfully booted Linux on VCU118 platform without DRAM…

July 2025: Project Inception

PowerCommons initiative launched with support from OpenPower Foundation…

💼 Seeking Partners & Support

Investors & Sponsors

We’re actively seeking funding partners who understand the strategic importance of sovereign computing infrastructure. PowerCommons offers:

• Strategic Returns: Position at the forefront of European digital sovereignty
• ESG Impact: Direct contribution to democratic technology and climate-friendly computing
• Technical Innovation: Access to cutting-edge open hardware development
• Market Opportunity: Growing demand for trustworthy computing in critical sectors

Sponsorship Range: €100K - €5M | Contact: sponsors@powercommons.org

Policy Makers & Government

Help shape the future of European digital sovereignty. We seek dialogue with:

• EU Commissioners for Digital Economy and Digital Single Market
• National CTOs and digital transformation officers
• Parliamentary Committees on technology and sovereignty
• Municipal Leaders implementing smart city initiatives

We’re particularly interested in connecting with leaders like:

• Margrethe Vestager (EU Competition & Digital)
• Roberto Viola (DG CONNECT)
• Thomas Fricke (Sovereign Tech Fund)
• Francesca Bria (Italian Innovation Fund)

Policy Brief Comong Soon | Contact: policy@powercommons.org

Speaking & Educational Opportunities

Our team is available for:

• 🎤 Conference Keynotes: Digital sovereignty, open hardware, post-capitalist technology
• 🏛️ Policy Forums: Technical briefings for decision makers
• 🎓 University Lectures: Computer architecture, open source hardware, sovereign computing
• 🏢 Corporate Workshops: Building secure infrastructure with open hardware

Topics: Open Hardware | Digital Sovereignty | Processor Architecture | Democratic Technology

Book a Speaker: speaking@powercommons.org

Academic Collaboration

Universities and research institutions are invited to:

• Joint Research: Formal verification, security analysis, architecture optimization
• Curriculum Integration: Use PowerCommons in computer architecture courses
• Student Projects: Bachelor/Master/PhD thesis opportunities
• Infrastructure Access: Remote FPGA boards for research and teaching

Academic Partnerships: academic@powercommons.org

🤲 Support the Commons

PowerCommons is a public interest technology project. Your support enables:

• 👨‍💻 Sustained development of open processors
• 🔬 Security audits and formal verification
• 📚 Documentation and educational materials
• 🌱 Community growth and outreach

Donate via: NLnet

PowerCommons is a public interest technology initiative aligned with European digital sovereignty goals and the principles of the commons.

Mission & Vision

Our Mission

To democratize high-performance computing by creating fully open, transparent, and verifiable processor architectures that serve as digital commons - collectively owned, democratically governed, and accessible to all.

PowerCommons develops and maintains open-source processor implementations, system architectures, and supporting infrastructure that eliminate proprietary dependencies, hidden functionalities, and corporate control over fundamental computing resources.

Our Vision

A Future of Sovereign Computing

We envision a world where:

• Every circuit is inspectable - No hidden management engines, no proprietary firmware, no unauditable code paths
• Communities control their infrastructure - Local sovereignty over digital resources, not dependency on foreign corporations
• Innovation serves humanity - Technology development guided by public interest, not surveillance capitalism
• Knowledge is truly free - Complete transparency from transistor to application, enabling genuine understanding and innovation

Join the Revolution

PowerCommons isn’t just building processors - we’re building the foundation for a democratic digital future. Every contribution, whether code, documentation, advocacy, or funding, advances our collective liberation from corporate control over computing.

The power of computing belongs to the people.

“The master’s tools will never dismantle the master’s house. We must build our own tools - transparent, democratic, and free.”
— Adapted from Audre Lorde for the digital age

Digital Sovereignty

Reclaiming Control Over Our Digital Infrastructure

Digital sovereignty is not merely about data localization or regulatory compliance - it’s about fundamental democratic control over the technologies that increasingly govern our lives. PowerCommons embodies this principle by creating computing infrastructure that communities can truly own, understand, and control.

The Crisis of Technological Dependence

Hidden Control Mechanisms

Every modern processor contains multiple layers of proprietary control:

• Management Engines: Intel ME, AMD PSP run below the operating system with full system access
• Proprietary Firmware: Unauditable code controlling critical functions
• Hardware Backdoors: Undocumented features accessible to manufacturers
• Supply Chain Vulnerabilities: Components from untrusted sources with unknown modifications

These mechanisms create fundamental vulnerabilities that no amount of software security can address.

Economic Extraction

The current computing paradigm extracts value through:

• Planned Obsolescence: Artificial limitations forcing constant upgrades
• Vendor Lock-in: Proprietary standards preventing migration
• Surveillance Capitalism: Data extraction as primary business model
• Rent-Seeking: Software-as-a-Service replacing ownership

PowerCommons breaks these extraction patterns by ensuring permanent ownership and control.

Technical Foundations of Sovereignty

Verifiable Security

True sovereignty requires the ability to verify every aspect of the system:

• Open Hardware: Every logic gate documented and inspectable
• Reproducible Builds: Identical outputs from source code
• Formal Verification: Mathematical proofs of security properties
• Transparent Supply Chain: Known origin of every component

Technological Independence

PowerCommons achieves independence through:

• No Proprietary Dependencies: Fully open stack from silicon to application
• Local Manufacturing Capability: Designs suitable for diverse fab processes
• Knowledge Transfer: Complete documentation and education
• Tool Chain Freedom: Open development tools throughout

Call to Action

For Policymakers

• Mandate Open Hardware: Require transparency in public procurement
• Fund Development: Support open processor initiatives
• Create Standards: Establish sovereignty requirements
• Build Capacity: Invest in local manufacturing

For Technologists

• Contribute Code: Develop open implementations
• Share Knowledge: Document and teach
• Build Tools: Create development infrastructure
• Form Networks: Connect with aligned projects

For Citizens

• Demand Transparency: Require open systems in public services
• Support Development: Contribute to funding campaigns
• Learn and Share: Understand and explain the importance
• Organize Locally: Build community technology initiatives

Resources

Essential Reading

• “The Age of Surveillance Capitalism” - Shoshana Zuboff
• “Radical Technologies” - Adam Greenfield
• “The Stack” - Benjamin Bratton
• “Platform Capitalism” - Nick Srnicek

Pioneering Organizations

• European Digital Rights (EDRi)
• Free Software Foundation Europe
• Chaos Computer Club
• La Quadrature du Net

Policy Documents

• EU Digital Sovereignty Strategy
• German Sovereign Tech Fund Charter
• Barcelona Digital Sovereignty Plan
• Amsterdam Digital Agenda

“Technology is the answer, but what was the question?”
— Cedric Price

The question is: How do we build technology that serves humanity rather than exploiting it? PowerCommons provides one answer: through radical transparency, democratic control, and the commons model.

Digital sovereignty is not a destination but a continuous process of reclaiming control over our technological future. Join us in building infrastructure for human flourishing rather than corporate extraction.

Why OpenPower

The Foundation for True Computing Freedom

A Proven Architecture with Deep Roots

OpenPower isn’t just another instruction set architecture - it’s a battle-tested technology with over 30 years of deployment in mission-critical systems. From the servers running banking infrastructure to the supercomputers modeling climate change, Power architecture has proven its reliability at scale.

Unlike emerging architectures that promise future potential, OpenPower delivers today with:

• Mature ecosystem: Decades of software support, tools, and expertise
• Production proven: Powers enterprise workloads globally
• Performance leadership: Consistently ranks in supercomputing top500
• Open governance: True community control through OpenPower Foundation

Comparison Matrix

Technical Superiority

Architecture Advantages

64-bit from the Ground Up
Power was designed as a 64-bit architecture from inception, not retrofitted like x86. This clean design yields:

• Consistent instruction encoding
• Efficient memory addressing
• Superior virtualization capabilities
• Hardware-enforced security boundaries

RISC Philosophy Done Right

• Fixed-length instructions for predictable decode
• Large register file (32 general purpose registers)
• Simple, orthogonal instruction set
• Powerful load/store architecture

Advanced Features

• Hardware transactional memory
• Decimal floating-point in hardware
• Advanced SIMD capabilities (VSX)
• Sophisticated branch prediction

Performance Characteristics

OpenPower processors excel in:

• Throughput Computing: Multiple execution units and deep pipelines
• Memory Bandwidth: Advanced cache hierarchies and memory controllers
• Parallel Processing: SMT4/SMT8 simultaneous multithreading
• Enterprise Reliability: ECC throughout, hardware error recovery

True Openness

While other architectures claim openness, OpenPower delivers:

Verification and Trust

With OpenPower’s open implementations:

• Every gate can be inspected
• No hidden backdoors possible
• Formal verification feasible
• Reproducible builds from source

Advisory Board

Leadership & Governance

PowerCommons operates under a collaborative governance model that balances technical expertise with democratic participation, ensuring our technology serves the public interest.

Executive Team

Project Lead

[Your Name]
Founder & Senior Engineer

LinkedIn | Matrix: @lead:matrix.org

Technical Advisory Board

Prof. Peter Hofstee

Chief Technical Advisor
IBM Fellow / Delft University of Technology

Architect of IBM’s Cell Broadband Engine processor that powered PlayStation 3 and early supercomputers. Leading expert in processor architecture with decades of experience in high-performance computing. Provides critical guidance on OpenPower architecture and system design.

Partner Organizations

Institutional Partners

• OpenPower Foundation - Technical standards and ecosystem

Strategic Advisory Council

Coming soon!

Community Partners

Building the Liberation Technology Ecosystem

PowerCommons thrives through collaboration with aligned organizations, communities, and initiatives working toward technological sovereignty, digital rights, and the commons.

Institutional Partners

OpenPower Foundation

Role: Technical Standards & Governance
Contribution: Architecture specifications, compliance testing, ecosystem coordination
Contact: openpowerfoundation.org

The OpenPower Foundation provides the technical and legal framework that makes PowerCommons possible. Their open governance model and patent pool ensure our work remains free and unencumbered.

NLnet Foundation

Role: Funding & European Advocacy
Contribution: Financial support, policy connections, sovereignty initiatives
Status: Proposals submitted, awaiting review

NLnet’s commitment to the open internet and European digital sovereignty aligns perfectly with PowerCommons’ mission.

Community Organizations

The Commune

Role: Post-Capitalist Technology Advocacy
Platform: Medium Publication
Focus: Critical analysis of technology under capitalism, alternative futures

The Commune provides essential political and philosophical context for why liberation technology matters.

The Sovereign Workshop

Role: Knowledge Dissemination
Format: Tutorials, workshops, documentation
Focus: Practical guides for building sovereign technology stacks

Transforming complex technical knowledge into accessible learning resources.

How to Become a Partner

For Organizations

1. Align with PowerCommons values and mission
2. Identify collaboration opportunities
3. Connect via partners@powercommons.org
4. Contribute through code, resources, or advocacy
5. Amplify the message of liberation technology

For Individuals

Join as a community partner by:

• Contributing code or documentation
• Organizing local events
• Translating materials
• Advocating for open hardware
• Teaching and mentoring

Partnership Principles

• Mutual Aid: Support flows in all directions
• Transparency: Open collaboration and communication
• Autonomy: Partners maintain independence
• Solidarity: United in liberation technology
• Sustainability: Long-term thinking and commitment

Current Needs

We’re actively seeking partners in:

• 🎓 Academic Research: Formal verification, security analysis
• 🏭 Manufacturing: PCB fabrication, ASIC production
• 💰 Funding: Grants, donations, sustainable revenue
• 🌍 Global Reach: Regional coordinators and translators
• 🛠️ Technical: FPGA experts, compiler developers
• 📢 Advocacy: Policy influence, public awareness

Partnership Benefits

• Early access to technology developments
• Influence on project direction
• Recognition in project materials
• Collaboration opportunities
• Shared resources and knowledge
• Building the commons together

Contact

General Partnership Inquiries: partners@powercommons.org
Academic Collaboration: academic@powercommons.org
Commercial Opportunities: commercial@powercommons.org
Community Organizations: community@powercommons.org

“Alone we can do so little; together we can do so much.” - Helen Keller

PowerCommons succeeds through the collective effort of partners committed to liberation technology. Join us in building the technological commons.

Projects Overview

Building the Open Computing Stack

PowerCommons develops interconnected projects that together create a complete, transparent, and sovereign computing platform. Each project advances specific technical goals while contributing to the larger vision of liberation technology.

Core Processor Projects

✅ Microwatt Xilinx VCU-118 Integration

Status: Complete | Delivered: September 2025

Successfully integrated Microwatt processor with enterprise-grade features, enabling Linux boot on modern FPGA platforms.

Achievements:

• Added VCU-118 support to Microwatt SoC (FuseSoC + VHDL). This additionally sets up LEDs to debug issues with clock, reset signal, UART etc.
• Extended Microwatt SoC LiteDRAM support to VCU-118 board
• Fixed LitexBios and LitexSoC to support Linux on Microwatt as Litex BIOS was only designed to boot RISC V.

Why It Matters: Established VCU-118 as the primary development platform for high-end OpenPower FPGA work.

Learn More → | Repository

🔥 PowerCommons A2O: OpenPower A2O Core Revival

Status: Active Development | Target: Q4 2025

Reviving IBM’s battle-tested A2O processor - the out-of-order superscalar core that powered Blue Gene/Q supercomputers. This enterprise-grade processor brings serious computational power to the open hardware ecosystem.

Key Objectives:

• Restore compatibility with modern FPGA toolchains
• Fix timing closure and synthesis issues
• Create comprehensive documentation
• Establish software toolchain

Why It Matters: A2O provides the high-performance computing capability needed for real-world workloads, from scientific computing to database servers.

Learn More → | Repository

🏗️ PowerCommons SoC Platform

Status: Architecture Phase | Target: 2026

Creating the world’s first fully open System-on-Chip with verifiable security from boot to application. Combines Microwatt (control) and A2O (compute) processors in a heterogeneous architecture.

Key Objectives:

• Integrate dual-core heterogeneous design
• Implement open BMC replacement
• Create secure boot architecture
• Develop complete firmware stack

Why It Matters: Eliminates the last proprietary components in modern computing systems, including the hidden management engines.

Learn More →

Project Integration Strategy

┌─────────────────────────────────────────────┐
│            PowerCommons Platform            │
├─────────────────────────────────────────────┤
│                                             │
│  ┌─────────────┐      ┌─────────────┐      │
│  │  Microwatt  │◄────►│     A2O     │      │
│  │   (Boot)    │      │  (Compute)  │      │
│  └─────────────┘      └─────────────┘      │
│         ▲                    ▲              │
│         └────────┬───────────┘              │
│                  ▼                          │
│         ┌─────────────┐                    │
│         │    LiteX    │                    │
│         │  Framework  │                    │
│         └─────────────┘                    │
│                  ▼                          │
│  ┌──────────────────────────────────┐      │
│  │     Peripherals & Memory         │      │
│  └──────────────────────────────────┘      │
│                                             │
└─────────────────────────────────────────────┘

“The future is not some place we are going, but one we are creating. The paths are not to be found, but made.” - John Schaar

Microwatt Integration

Open PowerPC Core on Modern FPGAs

Overview

Microwatt is an open-source PowerPC soft core developed by Anton Blanchard and IBM. PowerCommons has extended Microwatt to run on high end FPGA platforms with full Linux support.

Core: Microwatt v0.1
Architecture: PowerPC 64-bit
Platform: Xilinx VCU-118
Status: Linux operational

Development Work

Native Microwatt SoC

Implementation using Microwatt’s native build system (FuseSoC/VHDL):

• VCU-118 board support with debug capabilities
• DDR4 memory integration via LiteDRAM
• Linux boot from native Microwatt

Details →

LiteX Framework Integration

Integration of Microwatt into LiteX SoC framework:

• PowerPC support in LiteX BIOS
• Endianness and boot protocol fixes
• Linux boot through LiteX infrastructure

Details →

Key Achievements

Upstream Contributions

• Microwatt: VCU-118 platform support merged
• LiteX: PowerPC architecture fixes merged
• LiteDRAM: DDR4 timing configurations

Resources

• Microwatt Repository
• PowerCommons Fork
• Build Documentation

Microwatt SoC on VCU-118

Native Microwatt Implementation

Overview

Implementation of Microwatt SoC on Xilinx VCU-118 using the native Microwatt build system (FuseSoC/VHDL). This work established basic board support and added DDR4 memory capability.

Platform: Xilinx VCU-118 (XCVU9P FPGA)
Build System: FuseSoC
Language: VHDL

Task 1: VCU-118 Board Support with Debug LEDs

Objective

Add VCU-118 as a supported platform in Microwatt with GPIO-based debugging capabilities to diagnose bring-up issues.

Implementation

Created FuseSoC core files and VHDL top-level for VCU-118:

# Build commands
fusesoc run --target=vcu118 microwatt --ram_init_file=hello_world.hex

Debug LED mapping for hardware troubleshooting:

• LED 0: PLL lock status
• LED 1: Reset state
• LED 2-3: UART TX/RX activity
• LED 4-7: User-defined debug signals

-- Debug LED connections in top-level VHDL
leds(0) <= pll_locked;
leds(1) <= not soc_rst;
leds(2) <= uart_tx;
leds(3) <= uart_rx;

[Screenshot placeholder: VCU-118 board with LEDs showing successful clock lock]

Running Microwatt (No DRAM)

# Build the bitstream without DRAM
[Build command placeholder]

# Generate hello world binary
[Compile command placeholder]

# Program the FPGA
[Programming command placeholder]

# Connect to UART console
[Serial terminal command placeholder]

Challenges Solved

• Clock domain crossing from 300MHz input to 100MHz system clock
• Pin assignment for mixed voltage I/O standards
• Reset sequencing for stable initialization

Code: codeberg.org/PowerCommons/microwatt-vcu118

Task 2: LiteDRAM Integration

Objective

Integrate LiteDRAM DDR4 controller to access the VCU-118’s 4GB memory, enabling Linux boot.

Implementation

Extended the basic VCU-118 support with DDR4 memory:

# LiteDRAM configuration
class VCU118DDR4(Module):
    def __init__(self, sys_clk_freq=125e6):
        self.submodules.ddrphy = USDDRPHY(
            pads = platform.request("ddram"),
            memtype = "DDR4",
            sys_clk_freq = sys_clk_freq,
            cmd_latency = 1
        )

Memory initialization sequence:

1. Assert DDR4 reset for 500us minimum
2. Configure PHY with training patterns
3. Execute read/write leveling
4. Verify with memory test
5. Report status via UART

[Screenshot placeholder: Terminal showing DDR4 training completion and memory test pass]

Running Microwatt with DRAM

# Build Microwatt with LiteDRAM
[Build command with DRAM placeholder]

# Generate memory test binary
[Memory test compile placeholder]

# Program FPGA with DRAM support
[FPGA programming command placeholder]

# Run memory test
[Memory test execution placeholder]

# Load and boot Linux kernel
[Linux boot command placeholder]

Results

• Bandwidth: 1.6 GB/s sustained
• Size: 256MB mapped (4GB physical available)
• Stability: 48-hour memtest passed

Code: codeberg.org/PowerCommons/litedram-vcu118

LiteX SoC with Microwatt on VCU-118

PowerPC Support in LiteX Framework

Overview

Integration of Microwatt PowerPC core into the LiteX SoC framework, enabling Linux boot through LiteX’s infrastructure. This required fixing numerous RISC-V assumptions in LiteX.

Platform: Xilinx VCU-118
Framework: LiteX
CPU: Microwatt PowerPC

Task: PowerPC Boot Support in LiteX

Objective

Adapt LiteX SoC and BIOS to boot PowerPC Linux, fixing RISC-V assumptions throughout the codebase.

Implementation

Key fixes for PowerPC compatibility:

Endianness handling - PowerPC is big-endian:

// Fixed MMIO access for PowerPC
#ifdef __powerpc__
#define readl(addr) __builtin_bswap32(*(uint32_t *)(addr))
#define writel(val, addr) *(uint32_t *)(addr) = __builtin_bswap32(val)
#endif

Boot protocol - PowerPC uses function descriptors:

// Correct Linux entry for PowerPC
typedef struct {
    void *entry;
    void *toc;
} func_desc_t;

func_desc_t *desc = (func_desc_t *)KERNEL_ADDR;
void (*kernel_entry)(void) = desc->entry;

Memory layout - Fixed for PowerPC requirements:

• Kernel at 0x400000 (not RISC-V’s 0x40000000)
• Exception vectors at 0x0
• Device tree at 0xf00000

# Build and boot Linux
./build_kernel.sh
litex_term /dev/ttyUSB1 --kernel=linux.bin --kernel-adr=0x400000

[Screenshot placeholder: Linux boot messages on serial console]

Running Linux on LiteX/Microwatt

# Build LiteX SoC with Microwatt
[LiteX build command placeholder]

# Build Linux kernel for PowerPC
[Kernel build command placeholder]

# Build device tree
[DTB build command placeholder]

# Program FPGA with complete SoC
[FPGA programming placeholder]

# Boot Linux via serial terminal
[Linux serial boot command placeholder]

# Alternative: Boot from SPI flash
[SPI flash boot command placeholder]

Boot Performance

LiteX BIOS on Microwatt/VCU-118
CPU:    100MHz
RAM:    256MB
Kernel: 2.3MB loaded
Boot:   45 seconds to prompt

Bugs Fixed

• Wrong entry point handling for PowerPC
• Endianness issues in all MMIO access
• Memory barriers for PowerPC architecture
• Cache management operations
• Exception vector locations

Code: codeberg.org/PowerCommons/litex-powerpc

PowerCommons A2O - A2O Core Revival

Project Overview

The PowerCommons A2O initiative revives and modernizes IBM’s A2O processor core - a proven architecture that powered the world’s most powerful supercomputers. By making this enterprise-grade technology accessible on modern FPGA platforms, we’re democratizing access to high-performance, transparent computing.

Project Status: 🟡 Active Development
Timeline: September 2025 - March 2026 Funding: €50,000 (NLnet Foundation - pending)
Repository: codeberg.org/PowerCommons/powercommons-a2o

Why A2O?

Proven Heritage

The A2O processor isn’t experimental - it’s battle-tested technology that ran in production for years:

• Powered Blue Gene/Q supercomputers
• Achieved 16.32 petaflops in Sequoia system
• Demonstrated reliability at massive scale
• Optimized for power efficiency

Technical Excellence

• 64-bit PowerPC Architecture: Full ISA 2.06 compliance
• Out-of-Order Execution: Advanced performance optimization
• Multi-Threading: 4-way SMT capability
• Vector Processing: QPX floating-point unit
• Cache Hierarchy: Sophisticated L1/L2 cache design

Open Liberation

IBM released A2O as open source, but the code has suffered from:

• Incompatibility with modern toolchains
• Broken build systems
• Missing documentation
• Lack of community support

PowerCommons fixes these issues, making A2O accessible to everyone.

Technical Objectives

Phase 1: Infrastructure Setup (Months 1) 🚧✅

• Assess current codebase state
• Identify toolchain incompatibilities
• Document build requirements
• Establish development environment

Phase 2: Core Revival, Implementation & Software (Months 3-4) 🚧

• Fix Vivado 2025.x compatibility issues
• Resolve timing closure problems
• Update synthesis constraints
• Create automated build system

Phase 3: Integration and Documentation (Months 5-6) 📋

• Implement missing peripherals
• Add LiteX integration
• Create FPGA reference designs
• Roadmap

Current Challenges

Build System Issues

// Example of outdated synthesis directive
(* ram_style = "block" *)  // Vivado 2025 requires different syntax
reg [63:0] cache_data [0:1023];

The original build system uses obsolete Xilinx tools and scripts incompatible with modern Vivado versions.

Timing Closure

Critical paths in the original design exceed timing constraints on modern FPGAs:

• Cache access paths
• Out-of-order execution logic
• Vector unit operations

Software Stack

Limited software support requires development of:

• Modern GCC toolchain
• Linux kernel patches
• Bootloader implementation
• Debug infrastructure

Technical Specifications

Coming Soon!

Development Roadmap

Coming soon!

Build Instructions

Coming soon!

PowerCommons SoC

Complete Open Verifiable System-on-Chip

The Final Frontier of Open Hardware

PowerCommons SoC represents the culmination of our liberation technology vision: a complete computing system with zero proprietary components, from the smallest logic gate to the highest-level firmware. This isn’t just another open processor project - it’s the blueprint for truly sovereign computing infrastructure.

Architecture Overview

Heterogeneous Multi-Core Design

The PowerCommons SoC employs a heterogeneous architecture optimizing for both security and performance:

┌──────────────────────────────────────────────────────┐
│                 PowerCommons SoC                      │
├──────────────────────────────────────────────────────┤
│                                                       │
│  ┌──────────────┐         ┌──────────────────────┐   │
│  │  Microwatt   │◄───────►│      A2O Core       │   │
│  │  (Control)   │ AXI/WB. │    (Compute)        │   │
│  │              │         │                     │   │
│  │ - Boot       │         │ - Applications      │   │
│  │ - Security   │         │ - Linux OS          │   │
│  │ - BMC func   │         │ - User workloads    │   │
│  └──────────────┘         └──────────────────────┘   │
│         │                           │                │
│         └─────────┬─────────────────┘                │
│                   ▼                                  │
│        ┌─────────────────────┐                       │
│        │   Coherent NoC      │                       │
│        │   (LiteX Based)     │                       │
│        └─────────────────────┘                       │
│                   │                                  │
│    ┌──────────────┼──────────────┐                  │
│    ▼              ▼              ▼                  │
│ ┌──────┐    ┌──────────┐    ┌────────┐             │
│ │ DDR4 │    │ PCIe Gen3│    │  SATA  │             │
│ │ Ctrl │    │ Root Cplx│    │  Ctrl  │             │
│ └──────┘    └──────────┘    └────────┘             │
│                                                      │
│ ┌──────────────────────────────────────┐            │
│ │        Peripheral Subsystem          │            │
│ │ UART | SPI | I2C | GPIO | Ethernet   │            │
│ └──────────────────────────────────────┘            │
│                                                      │
└──────────────────────────────────────────────────────┘

Core Responsibilities

Microwatt Core (In-Order)

• First-stage bootloader
• Secure boot verification
• BMC functionality
• Power management
• Thermal control
• System monitoring
• Trust root

A2O Core (Out-of-Order)

• Operating system execution
• Application workloads
• High-performance computing
• Virtual machine hosting
• Database operations
• Scientific computing

PowerCommons SoC isn’t just another processor project - it’s the foundation for a new era of transparent, trustworthy computing. Every line of code, every logic gate, every design decision is open to inspection, modification, and improvement by the community it serves.

Architecture

Coming soon!

Security Model

Coming soon!

Integration Guide

Coming soon!

Funding Proposals

Current Funding Applications

PowerCommons seeks sustainable funding to develop fully open processor implementations that serve the public interest. Our funding strategy prioritizes grants that respect project autonomy while enabling ambitious technical development.

Submitted Proposals

Total Requested: €100,000

Funding Principles

• Independence: No corporate control or restrictive IP agreements
• Transparency: All funding sources and uses publicly disclosed
• Community Benefit: Funds advance open hardware for all
• Sustainability: Building long-term viability, not just short-term projects

How Funds Are Used

Development (70%)

Core developer compensation and critical infrastructure

Community (20%)

Documentation, education, and outreach

Operations (10%)

Administrative costs and contingency

All financial information is publicly disclosed in our quarterly transparency reports.

NL Net Foundation Funding Proposal PowerCommons A2O - OpenPower A2O Processor Revival Initiative

1. Project Overview and Expected Outcomes

Initially developed by IBM as part of the Blue Gene/Q supercomputing project, the OpenPower A2O processor represents a significant milestone in open-source computing architecture. This initiative aims to revive and modernize the A2O core, making it accessible for contemporary FPGA platforms and laying the foundation for future enterprise-grade computing, supercomputing solutions, and AI applications. Additionally, this is the fastest way to deliver a fully open-source and compliant CPU core built upon a proven architecture, decades of industry experience, and that can be easily modernized.

Technical Objectives: For this project, our primary goal is to restore full functionality to the A2O processor core, addressing build system incompatibilities, fixing broken build scripts with modern Vivado toolchains, addressing critical timing and synthesis issues, and eventually creating a robust software ecosystem around the processor. The project will deliver a working A2O implementation on modern Xilinx FPGA platforms, along with comprehensive documentation and a roadmap for ISA modernization and bringing the core in line with modern processor architectures (i.e., OpenPower ISA 3.1)

The A2O processor, in combination with a platform architecture that leverages the open-source and license-free MicroWatt OpenPOWER processor as the system boot processor and root of trust, can be utilized to create a fully open and verifiable SoC/system architecture. The system architecture aspect and MicroWatt-based platform architecture have been submitted in a companion proposal.

Current State and Challenges: The A2O processor code exists but suffers from bit rot - incompatible with current FPGA toolchains, undocumented build processes, and a lack of working software stacks. Our preliminary work has identified key technical barriers, including Vivado compatibility issues, missing peripheral implementations, and incomplete software and build toolchains. While some evidence exists that the core worked was barely functional on an FPGA board many years ago, it is unclear to what degree of functionality was tested and verified if at all. The comments and commit history in the OpenPower repository, paint a bleak picture.

Deliverables:

The working PowerCommons A2O core will be released in our public Git repository at:

2. Relevant Experience and Contributions

My involvement with OpenPower Foundation since May 2025 has provided hands-on expertise in OpenPower processor implementation, particularly through to the Microwatt project and broader ecosystem support.

Specific Technical Achievements

VCU118 Platform Enablement: I successfully added VCU118 FPGA board support to Microwatt SoC, enabling the processor to boot on this high-performance Xilinx platform. This required adapting the SoC infrastructure to the VCU118’s specific resources and constraints, including clock generation, I/O pin mappings, and resource utilization optimization.

DRAM Integration and Linux Boot: I further improved Microwatt Soc integration by adding support for VCU-118 DRAM controller transforming it from a demonstration core to a practical, Linux-capable system. This involved integrating DDR4 memory controllers, solving complex timing calibration issues. The successful Linux boot on VCU118 validated the complete hardware-software stack.

LiteX Framework Integration: While LiteX had limited Microwatt support, Linux boot was impossible as LiteX BIOS and bootstrapper only supported RISC-V. I enabled full Linux boot capability by::

• Adding PowerPC architecture support to the build system and BIOS
• Integrating new memory controller with proper timing calibration
• Resolving boot stack incompatibilities between LiteX and PowerPC
• Fixing interrupt controller memory region issues between Litex BIOS, Linux and Microwatt

These contributions established critical integration patterns that PowerCommons will extend for multi-core SoC development.

Community Infrastructure Support

I’ve assisted OpenPower community members in accessing multiple FPGA boards in remote environments, setting up:

• Board sharing protocols enabling 24/7 development across time zones
• Administering powercommons.org website and corresponding repositories
• Documentation and assisting new members

Open Source Contributions

My work has resulted in multiple upstream contributions:

• Microwatt repository: VCU118 platform support and DRAM integration
• LiteX repository: PowerPC architecture fixes and improvements
• Documentation: Setup guides and troubleshooting resources

You can refer to powercommons.org - I built and maintain the site along with build infrastructure and Git repositories.

This practical experience with real hardware, complex system integration, and community collaboration provides the foundation necessary to tackle PowerCommons’ ambitious goals of creating a fully open, verifiable SoC platform.

3. Budget Breakdown and Funding Utilization

We request a total funding of EUR 50,000. Note that the numbers below are indicative - given the highly complex nature of the project some funds may have to re-directed to secure equipment and/or licenses.

Budget Summary

Detailed Budget Breakdown

Personnel Costs (€40,000 - 80%)

The majority of the budget will cover daily expenses and compensation for project contributors. Given the specialized expertise required and budget constraints, the project will likely engage one primary contributor (myself), with the possibility of adding a second if a suitable candidate with deep technical knowledge can be identified at this rate. I might be the only contributor until additional funding can be secured.

Travel, Community and Dissemination (€7,000 - 14%)

Tools and Software (€2,000 - 4%)

Contingency and Administrative (€1,000 - 2%)

Task Breakdown by Phase

Additional Funding Sources

Currently, no other funding sources have been secured for this specific project. OpenPower Foundation provides in-kind support through expert consultation and community access. Future funding applications to the EU Horizon programs are planned for subsequent development phases.

The accelerated timeline requires higher daily rates to secure dedicated, experienced personnel capable of intensive development cycles within the compressed schedule.

4. Comparison with Historical Efforts

To the best of our knowledge, RISC-V and OpenPower are the only two widespread open source architectures. However, OpenPower and its parent Power Architectures have been around for much longer and are proven technologies. Additionally, OpenPower has a strict and well-established governance, compliance, and certification process, which makes it ideal for sensitive and highly secure environments.

In the long run, geopolitical considerations may influence the ecosystem, particularly given the geographic concentration of advanced RISC-V manufacturing and development capabilities. OpenPower Foundation, on the other hand, is a foundation with members from academia, industry, and the non-profit space from across the globe.

Greenfield vs Incremental

Previous OpenPower processor initiatives have predominantly been green field, individual-driven efforts, often constrained by single-person knowledge bottlenecks and limited institutional support. These projects attempted to design complete processors from scratch without fully leveraging existing, proven architectures.

Rather than starting from scratch, we build upon IBM’s proven A2O design - a member of the A2 family of processors that successfully powered Blue Gene/Q supercomputers. This foundation eliminates many fundamental design risks that plague ground-up processor projects. We aim to reuse and collaborate as much as possible, and deliver a working, open-core solution within a short timeframe. We then iterate and offer a modern version of the core in short sprints. We start with A2O, but we plan to integrate with and reuse the work that has already been delivered in projects like LiteX and LibreSoC, while complementing projects like PowerPC Notebook.

Our approach differs fundamentally through institutional backing from the OpenPower Foundation and direct guidance from Prof. Peter Hofstee, the original architect of IBM’s Cell Broadband Engine. This provides access to deep architectural knowledge that individual projects cannot replicate.

Key advantages include:

• Proven processor architecture with documented performance characteristics
• Direct access to original design expertise through Prof. Peter Hofstee
• OpenPower Foundation’s institutional support and community resources
• Focus on revival/modernization rather than complete redesign
• Intensive, professional development approach with compressed timeline
• Parallel effort on community building and involvement, working with the OpenPower Foundation

Formal verification opportunities

Unlike previous OpenPower processor initiatives that resulted in designs too complex for comprehensive formal verification, our approach creates unique opportunities for mathematical validation. MicroWatt, despite being a full-fledged 64-bit processor capable of booting Linux, maintains a remarkably small codebase (~20,000 lines of VHDL) that makes formal verification feasible. This compact yet powerful design enables us to pursue formal proofs of critical properties such as memory safety, instruction correctness, and absence of timing side-channels. By pairing the formally verifiable MicroWatt as a secure boot processor with the performance-oriented A2O core, PowerCommons can offer unprecedented security assurances—something impossible with proprietary processors or overly complex open designs like LibreSOC. This positions our project to deliver not just open hardware, but mathematically proven secure hardware, addressing critical infrastructure needs where verification is paramount.

5. Technical Challenges and Required Expertise

The A2O processor revival presents several significant technical challenges that require highly specialized expertise, combining multiple domains rarely found in a single individual.

FPGA Synthesis and Timing Closure: Modern FPGA toolchains have evolved significantly since A2O’s original implementation. Legacy Verilog code contains timing assumptions and synthesis directives incompatible with current Vivado versions. Resolving these requires a deep understanding of both processor microarchitecture and FPGA implementation strategies. Clock domain crossing, pipeline timing, and resource utilization optimization require expertise that bridges digital design and computer architecture.

Build System Modernization: The original A2O build environment uses obsolete scripts, dependency management, and compilation flows. Creating robust, reproducible build systems requires a combination of software engineering expertise and knowledge of hardware build tools. This includes makefile restructuring, dependency resolution, version control integration, and setting up continuous integration.

Software Toolchain Integration: Establishing working compiler toolchains, debuggers, and development tools requires expertise in compiler design, binary utilities, and processor instruction set architectures. The PowerPC instruction set implementation must be validated against processor behavior, requiring both software and hardware debugging capabilities.

System Integration and Peripheral Implementation: Integrating A2O with modern peripheral controllers, memory interfaces, and I/O systems requires expertise in systems engineering. This includes understanding bus protocols, interrupt handling, memory management units, and cache coherency implementations.

Linux Kernel Porting: Bringing up Linux on a revived A2O requires expertise in kernel internals, bootloader development, device tree configuration, and low-level system programming. Debugging kernel boot processes requires understanding both hardware behavior and operating system internals.

Accelerated Development Challenges: The compressed 6-month timeline intensifies these challenges, requiring rapid problem-solving capabilities and extensive parallel development workstreams. This requires exceptional project management skills, combined with technical expertise across all domains.

These challenges require a unique combination of computer architecture, FPGA design, system software, embedded programming, and intensive project management expertise—a skill set combination that is extremely rare and typically distributed across multiple specialists in industry settings.

6. Ecosystem Engagement and Deployment Strategy

Primary Ecosystem Actors

The OpenPower Foundation serves as our primary institutional partner, providing community access, technical guidance, and validation platforms. Their established relationships with hardware vendors, software developers, and research institutions create natural distribution channels for project outcomes.

Academic and research institutions are key targets for deployment, particularly those that require open-source, high-performance computing platforms for research and education. Universities with computer architecture programs benefit from accessible, well-documented processor implementations for teaching and research purposes.

Community Engagement Strategy

We will actively engage the broader OpenPower developer community through weekly technical updates, code contributions, and participation in foundation meetings. Monthly progress reports and quarterly technical demonstrations will maintain community visibility and gather feedback throughout the accelerated development cycle.

The FPGA development community, particularly those focused on open-source designs, represents another critical engagement target.

Industry Partnerships

Collaboration with FPGA board manufacturers ensures the availability of reference implementations on accessible development platforms. This includes partnerships with companies such as Digilent, Terasic, and others, which provide educational and development boards.

The retro computing community offers immediate deployment opportunities through specialized gaming and hobby computing applications. These users provide early adoption feedback and potential revenue streams, which are crucial for project sustainability.

PowerCommons SoC - Complete Open Verifiable System-on-Chip

Executive Summary

PowerCommons SoC represents a groundbreaking initiative to create the world’s first fully open, verifiable system-on-chip using OpenPower architecture. Building upon successful Microwatt and A2O processor implementations, this project delivers a complete computing platform with zero proprietary dependencies - from processor cores to firmware to board management controllers.

Project Duration: 12 months
Requested Funding: €50,000
Chief Technical Advisor: Prof. Peter Hofstee (IBM/Delft University of Technology)
Supporting Organization: OpenPower Foundation

Project Abstract

A complete, open, and verifiable SoC built using OpenPower Microwatt and A2O cores.

In the Power9 generation, IBM released a system reference design that included open firmware, which remains available today. However, that reference design relied on a board management controller (BMC) that was not open. While the OpenPOWER processor ISA is open and license-free, the Power9 implementation is not open-source and proprietary.

In this project, we aim to make progress towards a fully open, license-free, and verifiable SoC and system infrastructure. The LibreSOC project’s challenges stemmed from attempting novel processor architectures without sufficient hardware verification resources. In contrast, our project takes a more incremental approach, maximizing the leverage of existing fully open Power architecture cores, such as “Microwatt” and the “A2” family of cores, specifically the A2O out-of-order processor core, as well as open-source firmware infrastructure.

Our initial objective is to create a demonstrator of a fully open system architecture, including a fully open system software stack. This will provide a boost to multiple open hardware projects including the The PowerPC notebook project that pursued an open-system design, but eventually resorted to a commercial processor that is not open-source.

Project Overview and Expected Outcomes

PowerCommons SoC aims to create the world’s first fully open, verifiable system-on-chip using OpenPower architecture. Building on successful Microwatt and A2O implementations, we’ll deliver a complete computing platform with zero proprietary dependencies - from processor cores to firmware to board management. This proposal builds upon a companion proposal to bring OpenPower A2O processor to life under the PowerCommons umbrella. It reuses the A2O core brought back to life and couples it with Microwatt in an open, secure SoC.

Key Deliverables

Impact

This creates a trustworthy computing foundation for critical infrastructure, research institutions, and security-conscious organizations. Unlike existing “open” systems that hide proprietary components in firmware or management controllers, PowerCommons provides complete transparency and auditability.

Timeline

Success enables truly sovereign computing infrastructure free from hidden dependencies or backdoors.

2. Relevant Experience and Contributions

My involvement with OpenPower Foundation since May 2025 has provided hands-on expertise in OpenPower processor implementation, particularly through to the Microwatt project and broader ecosystem support.

Specific Technical Achievements

VCU118 Platform Enablement: I successfully added VCU118 FPGA board support to Microwatt SoC, enabling the processor to boot on this high-performance Xilinx platform. This required adapting the SoC infrastructure to the VCU118’s specific resources and constraints, including clock generation, I/O pin mappings, and resource utilization optimization.

DRAM Integration and Linux Boot: I further improved Microwatt Soc integration by adding support for VCU-118 DRAM controller transforming it from a demonstration core to a practical, Linux-capable system. This involved integrating DDR4 memory controllers, solving complex timing calibration issues. The successful Linux boot on VCU118 validated the complete hardware-software stack.

LiteX Framework Integration: While LiteX had limited Microwatt support, Linux boot was impossible as LiteX BIOS and bootstrapper only supported RISC-V. I enabled full Linux boot capability by::

• Adding PowerPC architecture support to the build system and BIOS
• Integrating new memory controller with proper timing calibration
• Resolving boot stack incompatibilities between LiteX and PowerPC
• Fixing interrupt controller memory region issues between Litex BIOS, Linux and Microwatt

These contributions established critical integration patterns that PowerCommons will extend for multi-core SoC development.

Community Infrastructure Support

I’ve assisted OpenPower community members in accessing multiple FPGA boards in remote environments, setting up:

• Board sharing protocols enabling 24/7 development across time zones
• Administering powercommons.org website and corresponding repositories
• Documentation and assisting new members

Open Source Contributions

My work has resulted in multiple upstream contributions:

• Microwatt repository: VCU118 platform support and DRAM integration
• LiteX repository: PowerPC architecture fixes and improvements
• Documentation: Setup guides and troubleshooting resources

You can refer to powercommons.org - I built and maintain the site along with build infrastructure and Git repositories.

This practical experience with real hardware, complex system integration, and community collaboration provides the foundation necessary to tackle PowerCommons’ ambitious goals of creating a fully open, verifiable SoC platform.

3. Budget Breakdown and Funding Utilization

We request a total funding of EUR 50,000. Note that the numbers below are indicative - given the highly complex nature of the project some funds may have to re-directed to secure equipment and/or licenses. Additionally, some costs might be shared with our companion proposal for bringing A2O core to life in case it is accepted leaving more room for personnel costs.

Budget Summary

Detailed Budget Breakdown

Personnel Costs (€40,000 - 80%)

I will serve as the lead developer while actively searching for an experienced contributor within the EU who is willing to work at these rates. Given the specialized expertise required and budget constraints, finding such a candidate may prove challenging. If we successfully identify a qualified second contributor with deep technical knowledge, the budget will be allocated between us. Otherwise, I will continue the work independently and allocate the personnel budget accordingly.

Verification and Testing (€2,500 - 5%)

Documentation and Dissemination (€1,000 - 2%)

Contingency and Flexible Allocation (€6,500 - 13%)

This contingency budget provides flexibility to address actual project needs as they arise, whether for hardware acquisition, additional tools, or unexpected technical challenges.

Other Funding Sources

The OpenPower Foundation provides in-kind support through technical expertise and testing infrastructure. No direct monetary funding is currently secured, though follow-on funding from EU Horizon Europe is planned for production implementation phases.

4. Comparison with Historical Efforts

PowerCommons represents a fundamental shift in approach compared to previous open processor initiatives. Where others attempted revolutionary designs or accepted proprietary components as necessary evils, we pursue evolutionary improvement while maintaining absolute openness.

Formal verification opportunities

Unlike previous OpenPower processor initiatives that resulted in designs too complex for comprehensive formal verification, our approach creates unique opportunities for mathematical validation. MicroWatt, despite being a full-fledged 64-bit processor capable of booting Linux, maintains a remarkably small codebase (~20,000 lines of VHDL) that makes formal verification feasible. This compact yet powerful design enables us to pursue formal proofs of critical properties such as memory safety, instruction correctness, and absence of timing side-channels. By pairing the formally verifiable MicroWatt as a secure boot processor with the performance-oriented A2O core, PowerCommons can offer unprecedented security assurances—something impossible with proprietary processors or overly complex open designs like LibreSOC. This positions our project to deliver not just open hardware, but mathematically proven secure hardware, addressing critical infrastructure needs where verification is paramount.

IBM Power9 Reference Design Limitations

IBM’s Power9 reference platform provided open firmware (Hostboot/Skiboot) but relied on proprietary ASPEED BMCs and, critically, the Power9 processor itself remained closed-source. Organizations deploying these systems must trust IBM’s implementation without ability to verify or modify processor behavior. PowerCommons eliminates these trust dependencies by using fully open processor cores whose every logic gate can be inspected and verified.

LibreSOC’s Overreach

LibreSOC attempted to create a novel hybrid CPU/GPU architecture with advanced vector processing capabilities. This revolutionary approach required solving multiple research-grade problems simultaneously:

• New instruction set extensions
• Novel microarchitecture designs
• Unproven synthesis techniques

The project struggled with verification complexity and lack of incremental validation milestones. PowerCommons instead leverages proven, working processor cores (Microwatt and A2O), focusing innovation on system integration rather than core architecture. This allows incremental validation at each integration stage.

PowerPC Notebook’s Integration Gaps

The PowerPC notebook project correctly identified market demand for open computing platforms but relied on NXP’s proprietary T2080 processor. While they developed open board designs and some firmware, the critical processor and its initialization sequences remained black boxes. PowerCommons ensures every component from transistor to application remains modifiable and maintainable by the community.

System76/Purism’s Partial Openness

Companies like System76 and Purism market “open” computers but rely entirely on proprietary Intel/AMD processors with Intel Management Engine or AMD Platform Security Processor. These hidden processors run unauditable code with full system access, negating security benefits of open firmware. PowerCommons provides genuine transparency with no hidden processors or unauditable code paths.

RISC-V Initiatives’ Fragmentation

While RISC-V offers an open ISA, implementations remain fragmented with varying degrees of openness. SiFive’s processors are proprietary, while open implementations like BOOM lack the maturity and ecosystem of OpenPOWER. Furthermore, the RISC-V ecosystem’s manufacturing and design capabilities are heavily concentrated in specific geographic regions, with the majority of commercial RISC-V development occurring in China. This concentration raises concerns for organizations requiring supply chain diversity and technological independence. PowerCommons benefits from OpenPOWER’s 30-year ecosystem maturity, extensive software support, proven enterprise deployments, and geographically distributed development community spanning Europe, North America, and other regions.

Our Differentiation

PowerCommons succeeds by:

1. Incremental complexity - Starting with working cores, adding integration layers progressively
2. Complete openness - No proprietary dependencies anywhere in the stack
3. Verification focus - Every component formally verifiable and reproducibly buildable
4. Ecosystem leverage - Building on OpenPOWER’s mature software ecosystem
5. Practical deployment - Targeting real use cases in security-critical applications

Unlike academic projects that prioritize novel research, or commercial efforts that accept proprietary components for convenience, PowerCommons delivers practical, fully open computing infrastructure. This positions it uniquely as the first genuinely trustworthy computing platform where every transistor’s behavior can be verified.

5. Technical Challenges

PowerCommons faces several interconnected technical challenges that push the boundaries of open hardware development while maintaining practical deployability.

Heterogeneous Multi-Core Integration

Integrating Microwatt (in-order, control-optimized) with A2O (out-of-order, compute-optimized) processors requires sophisticated cache coherency protocols and interconnect design. The processors have different pipeline depths, memory access patterns, and timing characteristics. Creating efficient communication between asymmetric cores while maintaining coherency requires careful protocol design and extensive verification.

Open BMC Implementation

Replacing proprietary BMCs represents uncharted territory in open hardware. BMCs handle critical functions including:

• Power sequencing
• Thermal management
• Fault detection
• Out-of-band management

Creating an open BMC requires implementing complex state machines for power management, developing thermal control algorithms, and ensuring fail-safe operation under all conditions. The BMC must monitor dozens of voltage rails, temperature sensors, and system health indicators while maintaining real-time response guarantees. This requires careful co-design of hardware monitoring capabilities and software control loops.

Firmware Stack Complexity

Adapting OpenPOWER’s Hostboot/Skiboot firmware for our open cores requires deep understanding of:

• Processor initialization sequences
• Memory training algorithms
• Secure boot flows

The firmware must handle differences between our implementation and IBM’s Power processors, including different cache sizes, TLB structures, and performance monitoring capabilities. Self-Boot Engine (SBE) equivalent functionality must be reimplemented for our open cores, handling early initialization before main firmware takes control.

Security Architecture Without Proprietary Elements

Implementing secure boot and attestation without proprietary security processors presents novel challenges. We must:

• Create hardware root of trust using open FPGA logic
• Implement cryptographic operations in verifiable hardware
• Ensure attack resistance without security-through-obscurity

This includes protecting against fault injection, side-channel attacks, and physical tampering while maintaining complete design transparency.

Performance Optimization Within FPGA Constraints

Achieving usable performance on FPGA platforms requires aggressive optimization across multiple dimensions. Clock frequency limitations of FPGAs (typically 100-200MHz) demand architectural optimizations to maintain acceptable performance. This includes:

• Implementing efficient cache hierarchies
• Optimizing critical paths
• Potentially adding specialized accelerators for common operations

Memory bandwidth limitations of FPGA boards require careful data flow optimization and potentially custom memory controllers.

Verification and Validation Complexity

Verifying correct operation of a complete SoC requires sophisticated methodologies combining:

• Formal verification
• Simulation
• Hardware testing

Cache coherency protocols must be formally proven correct, while system-level behaviors require extensive simulation. Creating comprehensive test suites that exercise all corner cases of multi-core interaction, interrupt handling, and error conditions requires significant effort. Hardware-software co-verification becomes critical when firmware depends on specific hardware behaviors.

Build System and Reproducibility

Ensuring reproducible builds across the entire stack - from HDL through firmware to operating system - requires sophisticated build system design. Different toolchains (Vivado for FPGA, GCC for firmware, Linux build systems) must be coordinated. Version management across hundreds of dependencies while maintaining build reproducibility demands careful infrastructure design. Supporting multiple FPGA targets with different resource constraints requires parameterizable designs and automated resource optimization.

Real-Time Operating Constraints

The BMC portion must maintain real-time guarantees for thermal management and fault response while running on resource-constrained soft processors. This requires:

• Careful RTOS selection or development
• Worst-case execution time analysis
• Interrupt latency optimization

Balancing real-time requirements with security features like secure boot verification adds additional complexity.

These challenges require expertise spanning computer architecture, FPGA design, embedded systems, security engineering, and formal verification - a combination rarely found in single teams. Our approach addresses this through modular design allowing parallel development, extensive reuse of proven components, and incremental integration with continuous validation.

6. Ecosystem Engagement

Core Ecosystem Partners

The OpenPOWER Foundation remains our primary ecosystem anchor, providing technical guidance, testing infrastructure, and community connections. Their working groups on security, firmware, and compliance ensure PowerCommons aligns with industry standards while pushing open hardware boundaries.

Academic and Research Engagement

Universities with hardware security research programs form natural early adopters, using PowerCommons for verifiable security research and education. We’ll establish partnerships with:

• [To be determined based on engagement]
• [Additional institutions to be identified]

These partnerships provide early access to designs and collaborative research opportunities. The reproducible builds and formal verification aspects appeal to academic researchers in formal methods and verification, creating opportunities for joint publications and tool development collaborations.

Government and Critical Infrastructure

European governmental agencies concerned with digital sovereignty represent key stakeholders. We’ll engage with initiatives like:

• Germany’s Sovereign Tech Fund
• [Additional agencies to be identified]

This positions PowerCommons as enabling truly sovereign computing infrastructure. Critical infrastructure operators requiring verifiable security - power grids, water systems, telecommunications - benefit from PowerCommons’ auditability. Early engagement with sector-specific security requirements ensures practical deployability.

Risk Mitigation Strategies

Technical Risks

• Multi-core integration complexity: Mitigated through incremental integration and extensive simulation
• BMC development challenges: Addressed by leveraging existing OpenBMC framework components
• Performance constraints: Managed through architectural optimization and selective hardware acceleration

Project Risks

• Schedule delays: Buffered through parallel development tracks and modular design
• Resource constraints: Mitigated through OpenPower Foundation support and community engagement
• Adoption barriers: Reduced through early stakeholder engagement and practical demonstrations

Contact

Connect with PowerCommons

Join the Liberation Technology Movement

Whether you’re a developer, researcher, advocate, or simply someone who believes in technological freedom, we want to hear from you. PowerCommons thrives through community collaboration and collective action.