WS8: Prefixed Instructions (Power ISA v3.1)

Owner: TBD Team Size: 2 engineers Duration: 10-12 weeks Priority: High (if targeting v3.1C)

💬 Discuss WS8: Join #powercommons:matrix.org to discuss prefixed instruction fetch, pipeline modifications, and v3.1 compliance.

Objectives

Support 64-bit prefixed instructions introduced in Power ISA v3.1.

Background

Power ISA v3.1 introduces prefixed instructions - a revolutionary change allowing 64-bit instructions:

• Prefix word (32 bits) + Suffix word (32 bits) = 64-bit instruction
• Enables 34-bit immediate operands (vs 16-bit in v3.0)
• Supports 64-bit PC-relative addressing
• Required for full v3.1C compliance

Why Prefixed Instructions Matter

1. Large Immediate Values: Load 34-bit constants without multiple instructions
2. Position Independent Code: Efficient PC-relative addressing for shared libraries
3. Future-Proofing: Foundation for future ISA extensions
4. Compiler Efficiency: Fewer instructions for address calculation

Instruction Format

Bits 0-1: '01' (indicates prefixed instruction)
Bits 2-5: Reserved
Bits 6-31: Prefix immediate/modifier (26 bits)
Bits 32-63: Standard 32-bit suffix instruction

Tasks

Pipeline and Fetch Modifications

Branch and PC Management

Implement Prefixed Instructions

Testing and Validation

Implementation Challenges

Challenge 1: I-Cache Fetch Width

Problem: A2 I-cache may fetch 32 bits per cycle Solution Options:

1. Fetch 64 bits per cycle (requires I-cache modification)
2. Fetch in two cycles (may impact frequency)
3. Prefetch buffer (add complexity)

Recommendation: Evaluate timing impact of 2-cycle fetch first

Challenge 2: Pipeline Bubble

Problem: Decoding prefix may take extra cycle Solution:

• Pipeline prefix decode in parallel with fetch of suffix
• Add instruction buffer stage
• May add 1 cycle penalty for prefixed instructions

Challenge 3: Exception Recovery

Problem: SRR0 must point to prefix, but pipeline may only know suffix PC Solution:

• Track “is_prefixed” flag through pipeline
• PC calculation: exception_pc = current_pc - (is_prefixed ? 8 : 4)

Challenge 4: Branch Prediction

Problem: PC advances by 4 or 8 depending on instruction Solution:

• Branch predictor must track instruction length
• BTB (Branch Target Buffer) needs “is_prefixed” bit
• May need to predict prefix indicator early

Performance Considerations

Frequency Impact

• Prefixed instruction path should not be on critical path
• Most instructions are still 32-bit
• Optimize for common case (non-prefixed)

Performance Benefit

• Reduces instruction count for:
  • Large immediate loads: 3 instructions → 1 instruction
  • GOT (Global Offset Table) access: 2 instructions → 1 instruction
  • Large struct field access: 2 instructions → 1 instruction

Estimated Improvement

• 5-10% fewer instructions for typical C code
• 10-15% fewer instructions for position-independent code
• Better code density

Dependencies

• WS1: Many prefixed instructions are load/store variants
• Should coordinate decoder changes with WS1 instruction additions
• Independent of WS3, WS4, WS2

Success Criteria

• All 18+ prefixed instructions implemented
• Correct PC handling (advances by 8 for prefixed)
• Correct exception handling (SRR0 points to prefix)
• I-cache handles prefixed instruction fetch
• Branch predictor works with prefixed instructions
• No frequency degradation
• Pass ISA compliance tests for prefixed instructions
• Linux kernel can use prefixed instructions

Testing Strategy

Unit Tests

• Individual prefixed instruction functionality
• Edge cases (alignment, boundaries)

Integration Tests

• Exception during prefixed instruction
• Branch prediction accuracy
• I-cache miss handling

System Tests

• Compile Linux kernel with GCC v3.1 support (uses prefixed instructions)
• Run applications compiled with -mcpu=power10
• Benchmark code density improvement

Documentation Requirements

• Architecture manual update: prefixed instruction support
• Programmer’s guide: when to use prefixed instructions
• Compiler integration guide
• Errata document: any limitations

Optional Enhancements

• Issue #369: Implement additional v3.1 prefixed instructions
  • pmxvi family (vector immediates)
  • Future-proofing for v3.1B features

References

• Power ISA v3.1C Book I, Chapter 1.6: Prefixed Instructions
• Power ISA v3.1C Book III, Chapter 1: Instruction Format
• GCC PowerPC backend: prefixed instruction generation
• Linux kernel: v3.1 instruction usage patterns

Decision: v3.0C vs v3.1C

If prefixed instructions are not implemented:

• ✅ Saves 10-12 weeks
• ✅ Simpler implementation
• ❌ Not v3.1 compliant
• ❌ Compiler support limited (GCC defaults to v3.1)
• ❌ Less efficient code generation

Recommendation: Implement WS8 for full v3.1C compliance and future-proofing.

Issues

Status: 9 open, 0 closed (0/9 complete)

Last updated: 2025-12-05 16:48:17