WS6: Performance Monitor Unit
Owner: TBD Team Size: 1-2 engineers Duration: 6-8 weeks Priority: Medium
💬 Discuss WS6: Join #powercommons:matrix.org to discuss PMU architecture, event mappings, and Linux perf integration.
Objectives
Replace implementation-specific PMU with architected ISA v3.1C PMU.
Background
The A2 core currently implements A2-specific performance monitoring registers (AESR, CESR, IESR, MESR, XESR). To achieve ISA v3.1C compliance, we need to replace these with the architected Performance Monitor Unit (PMU) defined in Book III-S.
The architected PMU provides:
- Standardized interface: MMCR0/1/2/A control registers
- Six performance counters: PMC1-6 (SPR 771-776)
- Event sampling: SIER for sampled instruction data
- Portability: Standard event codes across POWER implementations
- Linux perf support: Required for
perfcommand and performance analysis
Tasks
Remove A2-Specific PMU Registers
Implement Architected PMU Registers
Event Mapping
Testing and Validation
Implementation Notes
Counter Overflow Handling
When PMC[i] overflows (bit 0 transitions from 0 to 1):
1. Set MMCR0[PMAO] (alert occurred)
2. If MMCR0[PMAE]=1, trigger Performance Monitor Interrupt
3. Freeze counters if MMCR0[FCECE]=1
4. Sample instruction data into SIER if enabled
Performance Monitor Interrupt
- Vector: 0xF00 (Performance Monitor Exception)
- Saves PC in SRR0
- Must be enabled via MSR[EE] and MMCR0[PMAE]
- Critical for profiling tools
Linux Integration
The architected PMU enables:
perf stat- hardware counter statisticsperf record- sampling-based profilingperf top- real-time profilingperf annotate- instruction-level profiling
Register Summary
| SPR Number | Register | Purpose |
|---|---|---|
| 768 | SIER | Sampled Instruction Event Register |
| 769 | MMCR2 | Monitor Mode Control Register 2 |
| 770 | MMCR1, MMCRA | Monitor Mode Control Registers |
| 771-776 | PMC1-6 | Performance Monitor Counters |
| 779 | MMCR0 | Monitor Mode Control Register 0 |
Dependencies
- None (can start immediately)
- Parallel with WS1, WS3, WS4
Success Criteria
- All A2-specific PMU registers removed
- All architected PMU registers implemented
- At least 10 architected events supported
- PMU interrupts working correctly
- Counters count accurately (verified against RTL simulation)
- Linux
perfcommand works on A2 core - Pass ISA compliance PMU tests
Performance Impact
- Minimal impact on core frequency
- Counters run in parallel with execution
- Event detection should not be on critical timing path
- Target: No frequency degradation
Documentation Requirements
- User Manual chapter on Performance Monitoring
- List all supported events with descriptions
- Example code for programming PMU
- Performance monitoring best practices
Open Questions
- Event Selection: Which architected events are feasible to implement in A2?
- Sampling Frequency: What is acceptable overhead for SIER sampling?
- Backwards Compatibility: Do we provide emulation for old A2 PMU registers?
References
- Power ISA v3.1C Book III-S, Chapter 4: Performance Monitor
- OpenPOWER ELF v2 ABI: PMU Programming Interface
- Linux kernel:
arch/powerpc/perf/implementation - IBM POWER PMU documentation
Issues
Status: 10 open, 0 closed (0/10 complete)
| # | Title | Category | Tags | Status | Priority | Assignee |
|---|---|---|---|---|---|---|
| #49 | Remove AESR, CESR, IESR1-2, MESR1-2, XESR1-2 registers | General | - | ⬜ Open | 🟡 Medium | - |
| #50 | Implement PMC1-6 registers | General | - | ⬜ Open | 🟡 Medium | - |
| #51 | Implement MMCR0 register | General | - | ⬜ Open | 🟡 Medium | - |
| #52 | Implement MMCR1 register | General | - | ⬜ Open | 🟡 Medium | - |
| #53 | Implement MMCR2 register | General | - | ⬜ Open | 🟡 Medium | - |
| #54 | Implement MMCRA register | General | - | ⬜ Open | 🟡 Medium | - |
| #55 | Implement SIER register | General | - | ⬜ Open | 🟡 Medium | - |
| #56 | Implement architected event selection | General | - | ⬜ Open | 🟡 Medium | - |
| #57 | Add implementation-specific events | General | - | ⬜ Open | 🟡 Medium | - |
| #58 | Create PMU test suite | General | - | ⬜ Open | 🟡 Medium | - |
Last updated: 2025-12-05 16:48:17