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WS3: Interrupt Architecture

Owner: TBD Duration: 10-12 weeks Priority: Critical

💬 Discuss WS3: Join #powercommons:matrix.org to discuss interrupt vector migration, HSRR0/1 implementation, and scv/rfscv strategies.

Objectives

Migrate from Book III-E interrupt model to ISA v3.0C/v3.1C interrupt architecture.

Deliverables

  1. Replace multiple save/restore register sets with HSRR0/1
  2. Implement rfid and hrfid instructions
  3. Remove IVPR/GIVPR, implement LPCR[AIL]/[HAIL]
  4. Implement scv/rfscv instructions
  5. Update interrupt vectors per ISA

Roadmap

Phase 1: Analysis (Weeks 1-2)

  • Map Book III-E to Book III-S interrupt differences
  • Design new interrupt flow
  • Plan SPR transitions

Phase 2: Save/Restore Logic (Weeks 3-6)

  • Remove GSRR0/1, CSRR0/1, MCSRR0/1
  • Remove rfgi, rfci, rfmci instructions
  • Implement hrfid

Phase 3: Vector Control (Weeks 7-9)

  • Remove IVPR/GIVPR
  • Implement LPCR[AIL]/[HAIL]
  • Update vector address calculation

Phase 4: New Instructions (Weeks 10-11)

  • Implement scv/rfscv

Phase 5: Integration (Weeks 12)

  • System testing
  • Performance validation

Dependencies

  • WS2: Hypervisor facilities (HSRR0/1, LPCR, MSR[HV])

Risks

  1. Interrupt priority changes may affect real-time behavior
  2. Vector address calculation complexity
  3. Interaction with hypervisor interrupt routing

Success Criteria

  • All Book III-E interrupt mechanisms removed
  • ISA-compliant interrupt vectors
  • scv/rfscv functional
  • LPCR[AIL]/[HAIL] operational
  • Pass ISA interrupt compliance tests
  • Interrupt latency within 5% of baseline

Issues

Status: 27 open, 0 closed (0/27 complete)

#TitleCategoryTagsStatusPriorityAssignee
#120Remove GSRR0/GSRR1 registersInterruptcleanup, interrupt, registers⬜ Open🟠 High-
#121Remove CSRR0/CSRR1 registersInterruptcleanup, interrupt, registers⬜ Open🟠 High-
#122Remove MCSRR0/MCSRR1 registersInterruptcleanup, interrupt, registers⬜ Open🟠 High-
#123Update SRR0/SRR1 usageInterruptinterrupt, registers⬜ Open🟠 High-
#124Replace rfi with rfidInterruptinstruction, interrupt⬜ Open🟠 High-
#125Implement hrfid instructionInterrupthypervisor, instruction, interrupt⬜ Open🟠 High-
#126Remove rfgi instructionInterruptcleanup, instruction, interrupt⬜ Open🟠 High-
#127Remove rfci instructionInterruptcleanup, instruction, interrupt⬜ Open🟠 High-
#128Remove rfmci instructionInterruptcleanup, instruction, interrupt⬜ Open🟠 High-
#129Remove rfdi instruction (if exists)Interruptcleanup, instruction, interrupt⬜ Open🟢 Low-
#130Remove IVPR registerInterruptcleanup, interrupt, registers⬜ Open🟠 High-
#131Remove GIVPR registerInterruptcleanup, interrupt, registers⬜ Open🟠 High-
#132Remove IVOR registersInterruptcleanup, interrupt, registers⬜ Open🟠 High-
#133Implement LPCR[AIL] functionalityInterruptinterrupt, lpar⬜ Open🟠 High-
#134Implement LPCR[HAIL] functionalityInterrupthypervisor, interrupt, lpar⬜ Open🟡 Medium-
#135Update interrupt vector offsets per ISAInterruptinterrupt, vectors⬜ Open🟠 High-
#136Implement Hypervisor-specific interrupt vectorsInterrupthypervisor, interrupt, vectors⬜ Open🟠 High-
#137Implement scv instructionInterruptinstruction, interrupt, syscall⬜ Open🟠 High-
#138Implement rfscv instructionInterruptinstruction, interrupt, syscall⬜ Open🟠 High-
#139Update sc instruction per ISAInterruptinstruction, interrupt, syscall⬜ Open🟠 High-
#140Remove wrtee instructionInterruptcleanup, instruction, interrupt⬜ Open🟠 High-
#141Remove wrteei instructionInterruptcleanup, instruction, interrupt⬜ Open🟠 High-
#142Update machine check architectureInterruptinterrupt, machine-check⬜ Open🟠 High-
#143Update DSISR register formatInterruptinterrupt, registers⬜ Open🟡 Medium-
#144Update SRR1 bit layout for interruptsInterruptinterrupt, registers⬜ Open🟡 Medium-
#145Create interrupt architecture test suiteVerificationtesting, verification⬜ Open🟠 High-
#146Interrupt performance characterizationPerformanceperformance, verification⬜ Open🟡 Medium-

Last updated: 2025-12-05 16:48:17