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WS4: Storage Management (MMU/Radix Translation)

Owner: TBD Duration: 20-24 weeks Priority: Critical

💬 Discuss WS4: This is a critical workstream! Join #powercommons:matrix.org to discuss radix tree translation, page walker design, and two-level LPAR support.

Objectives

Replace Book III-E TLB-based MMU with ISA v3.0C/v3.1C radix tree translation, including two-level (radix-on-radix) support for LPAR.

Deliverables

  1. Radix tree page table walker
  2. Page walk cache implementation
  3. Two-level translation for LPAR
  4. PTCR, partition table, process table
  5. New TLB management instructions
  6. Removal of Book III-E MMU

Roadmap

Phase 1: Architecture & Design (Weeks 1-4)

  • Study ISA radix translation
  • Design page walker architecture
  • Design page walk cache
  • Plan TLB integration

Phase 2: Single-Level Radix (Weeks 5-12)

  • Implement partition/process tables
  • Implement radix page walker
  • Implement page walk cache
  • Basic TLB integration

Phase 3: Two-Level Translation (Weeks 13-18)

  • Implement nested radix translation
  • Update page walker for 2-level
  • Update page walk cache

Phase 4: Cleanup & Optimization (Weeks 19-22)

  • Remove Book III-E MMU
  • Performance optimization
  • TLB management updates

Phase 5: Integration (Weeks 23-24)

  • Full system testing
  • Performance validation

Dependencies

  • WS2: Hypervisor facilities (LPIDR, LPCR)
  • Memory subsystem for page walker
  • TLB hardware

Risks

  1. High Complexity: Radix walker with two-level translation is complex
  2. Performance: Page walk latency could be high without good caching
  3. Verification: Comprehensive testing required for correctness
  4. Schedule: Most time-consuming workstream, likely on critical path

Success Criteria

  • Radix page walker functional for all page sizes
  • Two-level translation working for LPAR
  • Page walk cache achieves >90% hit rate
  • TLB management instructions compliant
  • All Book III-E MMU removed
  • Pass ISA MMU compliance tests
  • Linux boots with radix translation
  • TLB miss latency <100 cycles (with cache hits)

Issues

Status: 40 open, 0 closed (0/40 complete)

#TitleCategoryTagsStatusPriorityAssignee
#500Design radix page table walker architectureMmuarchitecture, design, mmu⬜ Open🔴 Critical-
#501Design page walk cache architectureMmuarchitecture, cache, design, mmu⬜ Open🔴 Critical-
#502Implement PTCR registerMmummu, registers, spr⬜ Open🔴 Critical-
#503Implement partition table logicMmummu, partition-table⬜ Open🔴 Critical-
#504Implement process table logicMmummu, process-table⬜ Open🔴 Critical-
#505Implement PID registerMmummu, registers, spr⬜ Open🟠 High-
#506Implement radix page table walker state machineMmummu, page-walker⬜ Open🔴 Critical-
#507Implement memory interface for page walkerMmumemory, mmu, page-walker⬜ Open🔴 Critical-
#508Implement page size supportMmummu, page-walker⬜ Open🟠 High-
#509Implement reference and change bit handlingMmummu, page-walker⬜ Open🟠 High-
#510Implement permission checkingMmummu, page-walker, security⬜ Open🟠 High-
#511Implement page walk cache structureMmucache, mmu, performance⬜ Open🔴 Critical-
#512Integrate page walk cache with walkerMmucache, mmu, page-walker⬜ Open🔴 Critical-
#513Implement page walk cache invalidationMmucache, mmu, tlb-management⬜ Open🟠 High-
#514Design two-level translation architectureMmuarchitecture, design, lpar, mmu⬜ Open🔴 Critical-
#515Implement guest (L1) radix walkerMmulpar, mmu, page-walker⬜ Open🔴 Critical-
#516Implement host (L2) radix walker for nested translationMmulpar, mmu, page-walker⬜ Open🔴 Critical-
#517Implement nested page walk cacheMmucache, lpar, mmu, performance⬜ Open🟠 High-
#518Implement TLB fill from page walkerMmummu, page-walker, tlb⬜ Open🔴 Critical-
#519Implement TLB miss handling flowMmummu, page-walker, tlb⬜ Open🔴 Critical-
#520Implement tlbie instructionMmuinstruction, mmu, tlb-management⬜ Open🔴 Critical-
#521Implement tlbiel instructionMmuinstruction, mmu, tlb-management⬜ Open🟠 High-
#522Remove DEAR register, migrate to DARMmucleanup, mmu, registers⬜ Open🟠 High-
#523Remove ESR register, migrate to DSISRMmucleanup, mmu, registers⬜ Open🟠 High-
#524Remove MAS registers (MAS0-8)Mmucleanup, mmu, registers⬜ Open🟠 High-
#525Remove TLB0CFG, TLB0PS, EPTCFG registersMmucleanup, mmu, registers⬜ Open🟡 Medium-
#526Remove LRATCFG, LRATPS, LPER, LPERU registersMmucleanup, mmu, registers⬜ Open🟡 Medium-
#527Remove EPLC, EPSC registersMmucleanup, mmu, registers⬜ Open🟡 Medium-
#528Remove eratilx, erativax, eratre, eratsrx, eratsx, eratwe instructionsMmucleanup, instruction, mmu⬜ Open🟠 High-
#529Remove tlbilx, tlbivax, tlbre, tlbsrx, tlbsx, tlbwe instructionsMmucleanup, instruction, mmu⬜ Open🟠 High-
#530Remove external PID facilityMmucleanup, external-pid, mmu⬜ Open🟡 Medium-
#531Change endianness from per-page to global (MSR[LE])Mmuendianness, mmu⬜ Open🟠 High-
#532Create radix MMU test suiteVerificationmmu, testing, verification⬜ Open🔴 Critical-
#533Update TLB structure for radixMmummu, tlb⬜ Open🔴 Critical-
#534Implement slbia instruction (if needed)Mmuinstruction, mmu, tlb-management⬜ Open🟢 Low-
#535Remove MMUCFG, MMUCR0-3, MMUCSR0 registersMmucleanup, mmu, registers⬜ Open🟠 High-
#536Update alignment interrupt conditions per ISAMmualignment, interrupt, mmu⬜ Open🟡 Medium-
#537Create LPAR MMU isolation testsVerificationlpar, mmu, testing, verification⬜ Open🟠 High-
#538MMU performance characterizationPerformancemmu, performance, verification⬜ Open🟠 High-
#539Linux boot test with radix MMUVerificationintegration, mmu, testing, verification⬜ Open🔴 Critical-

Last updated: 2025-12-05 16:48:17