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WS2: Hypervisor & Virtualization Facilities

Owner: TBD Duration: 16-20 weeks Priority: Critical

💬 Discuss WS2: Join #powercommons:matrix.org to discuss LPAR implementation, hypervisor state transitions, and KVM enablement strategies.

Objectives

Transform embedded hypervisor model (Book III-E) to ISA v3.0C/v3.1C hypervisor/LPAR model.

Deliverables

  1. MSR[HV] bit implementation (replacing MSR[GS])
  2. LPAR support with LPCR, HRMOR, PCR
  3. Hypervisor-specific SPRs (HSRR0/1, HSPRG0/1, HDAR, HDSISR)
  4. Per-thread partition support
  5. Hypervisor Emulation Assist Interrupt (HEAI)

Roadmap

Phase 1: Architecture Study (Weeks 1-2)

  • Analyze Book III-E vs Book III-S differences
  • Design state transition model
  • Plan SPR remapping

Phase 2: Core State Logic (Weeks 3-8)

  • Implement MSR[HV] bit
  • Remove MSR[GS] logic
  • Rework privilege checking

Phase 3: SPR Implementation (Weeks 9-13)

  • Implement new hypervisor SPRs
  • Remove embedded hypervisor SPRs
  • Update SPR access control

Phase 4: LPAR Support (Weeks 14-17)

  • Implement LPCR/HRMOR/PCR
  • Add per-thread partition support
  • Implement HEAI

Phase 5: Integration (Weeks 18-20)

  • System-level testing
  • KVM validation
  • Performance optimization

Dependencies

  • WS3: Interrupt Architecture (interrupt routing changes)
  • WS4: Storage Management (LPIDR integration with MMU)

Risks

  1. Per-thread partition support adds significant complexity
  2. KVM compatibility issues
  3. Privilege state transition bugs
  4. Performance degradation in partition switching

Success Criteria

  • MSR[HV] operational, MSR[GS] removed
  • All hypervisor SPRs implemented
  • LPAR fully functional
  • Per-thread partitioning working
  • KVM boots and runs guests
  • Pass ISA hypervisor compliance tests
  • <10% overhead for partition switching

Issues

Status: 27 open, 0 closed (0/27 complete)

#TitleCategoryTagsStatusPriorityAssignee
#94Replace MSR[GS] with MSR[HV]Hypervisorarchitecture, hypervisor, msr⬜ Open🔴 Critical-
#95Remove guest state SPR mappingHypervisorhypervisor, spr⬜ Open🔴 Critical-
#96Implement privilege state logic per ISA v3.1CHypervisorhypervisor, privilege⬜ Open🔴 Critical-
#97Implement HSRR0/HSRR1 registersHypervisorhypervisor, registers, spr⬜ Open🟠 High-
#98Implement HSPRG0/HSPRG1 registersHypervisorhypervisor, registers, spr⬜ Open🟠 High-
#99Implement HDAR registerHypervisorhypervisor, registers, spr⬜ Open🟠 High-
#100Implement HDSISR registerHypervisorhypervisor, registers, spr⬜ Open🟠 High-
#101Implement HEIR registerHypervisorhypervisor, registers, spr⬜ Open🟠 High-
#102Implement HEIR registerHypervisorhypervisor, registers, spr⬜ Open🟠 High-
#103Implement LPCR registerHypervisorhypervisor, lpar, spr⬜ Open🔴 Critical-
#104Implement HRMOR registerHypervisorhypervisor, lpar, spr⬜ Open🔴 Critical-
#105Implement PCR registerHypervisorcompatibility, hypervisor, lpar, spr⬜ Open🟡 Medium-
#106Remove EPCR registerCleanupcleanup, embedded-hv⬜ Open🟠 High-
#107Remove MSRP registerCleanupcleanup, embedded-hv⬜ Open🟠 High-
#108Remove GESR, GDEAR registersCleanupcleanup, embedded-hv⬜ Open🟡 Medium-
#109Remove ehpriv instructionCleanupcleanup, embedded-hv, instruction⬜ Open🟠 High-
#110Modify sc (system call) instructionHypervisorhypervisor, system-call⬜ Open🟠 High-
#111Implement Hypervisor Emulation Assist Interrupt (HEAI)Hypervisorhypervisor, interrupt⬜ Open🟠 High-
#112Implement privilege violation routing per LPCR[EVIRT]Hypervisorhypervisor, interrupt, privilege⬜ Open🟠 High-
#113Update interrupt delivery for guest vs hypervisorHypervisorhypervisor, interrupt⬜ Open🟠 High-
#114Remove per-core partition restrictionHypervisorhypervisor, lpar, multi-threading⬜ Open🔴 Critical-
#115Implement per-thread LPIDRHypervisorhypervisor, lpar, multi-threading⬜ Open🟠 High-
#116Create hypervisor privilege state test suiteVerificationtesting, verification⬜ Open🟠 High-
#117Create LPAR isolation test suiteVerificationlpar, testing, verification⬜ Open🟠 High-
#118KVM integration testingVerificationkvm, testing, verification⬜ Open🔴 Critical-
#119Hypervisor performance optimizationPerformanceoptimization, performance⬜ Open🟡 Medium-
#499Replace MSR[GS] with MSR[HV]Hypervisorarchitecture, hypervisor, msr⬜ Open🔴 Critical-

Last updated: 2025-12-05 16:48:17