Microwatt SoC on VCU-118

Native Microwatt Implementation

Overview

Implementation of Microwatt SoC on Xilinx VCU-118 using the native Microwatt build system (FuseSoC/VHDL). This work established basic board support and added DDR4 memory capability.

Platform: Xilinx VCU-118 (XCVU9P FPGA)
Build System: FuseSoC
Language: VHDL

Task 1: VCU-118 Board Support with Debug LEDs

Objective

Add VCU-118 as a supported platform in Microwatt with GPIO-based debugging capabilities to diagnose bring-up issues.

Implementation

Created FuseSoC core files and VHDL top-level for VCU-118:

# Build commands
fusesoc run --target=vcu118 microwatt --ram_init_file=hello_world.hex

Debug LED mapping for hardware troubleshooting:

• LED 0: PLL lock status
• LED 1: Reset state
• LED 2-3: UART TX/RX activity
• LED 4-7: User-defined debug signals

-- Debug LED connections in top-level VHDL
leds(0) <= pll_locked;
leds(1) <= not soc_rst;
leds(2) <= uart_tx;
leds(3) <= uart_rx;

[Screenshot placeholder: VCU-118 board with LEDs showing successful clock lock]

Running Microwatt (No DRAM)

# Build the bitstream without DRAM
[Build command placeholder]

# Generate hello world binary
[Compile command placeholder]

# Program the FPGA
[Programming command placeholder]

# Connect to UART console
[Serial terminal command placeholder]

Challenges Solved

• Clock domain crossing from 300MHz input to 100MHz system clock
• Pin assignment for mixed voltage I/O standards
• Reset sequencing for stable initialization

Code: codeberg.org/PowerCommons/microwatt-vcu118

Task 2: LiteDRAM Integration

Objective

Integrate LiteDRAM DDR4 controller to access the VCU-118’s 4GB memory, enabling Linux boot.

Implementation

Extended the basic VCU-118 support with DDR4 memory:

# LiteDRAM configuration
class VCU118DDR4(Module):
    def __init__(self, sys_clk_freq=125e6):
        self.submodules.ddrphy = USDDRPHY(
            pads = platform.request("ddram"),
            memtype = "DDR4",
            sys_clk_freq = sys_clk_freq,
            cmd_latency = 1
        )

Memory initialization sequence:

1. Assert DDR4 reset for 500us minimum
2. Configure PHY with training patterns
3. Execute read/write leveling
4. Verify with memory test
5. Report status via UART

[Screenshot placeholder: Terminal showing DDR4 training completion and memory test pass]

Running Microwatt with DRAM

# Build Microwatt with LiteDRAM
[Build command with DRAM placeholder]

# Generate memory test binary
[Memory test compile placeholder]

# Program FPGA with DRAM support
[FPGA programming command placeholder]

# Run memory test
[Memory test execution placeholder]

# Load and boot Linux kernel
[Linux boot command placeholder]

Results

• Bandwidth: 1.6 GB/s sustained
• Size: 256MB mapped (4GB physical available)
• Stability: 48-hour memtest passed

Code: codeberg.org/PowerCommons/litedram-vcu118