Quick Start
Get Microwatt running on Litex Soc and boot Linux on Xilinx VCU 118 FPGA in under 30 minutes using prebuilt resources.
💬 Need Help? Stuck or have questions? Join #powercommons:matrix.org for real-time support from the community!
Prerequisites
- FPGA board with USB cable - we’ve only tested Xilinx VCU-118. Arty A7 100T support coming soon.
- You have already setup a PowerCommons WSL instance following the WSL Setup instructions or have an equivalent Linux setup.
- Vivado is not required for quickstart.
Steps
1. Download Prebuilt Bitstream and Linux images
Depending upon your end goal, download the corresponding bitstream. For example, if you want to see linux boot on the VCU 118 board with Litex SoC, download the following bitstream and linux image: For Xilinx VCU 118, download the following bitstream:
Download bitstream for Microwatt on Litex SoC microwatt-litex-vcu118-dram-2026-02-25.bit:
curl -O https://codeberg.org/PowerCommons/Releases/releases/download/vcu118-20260225/microwatt-litex-vcu118-dram-2026-02-25.bit
Download linux:
curl -O https://codeberg.org/PowerCommons/Releases/releases/download/vcu118-20260225/linux-6.12.0-litex-2026-02-25.dtbImage.microwatt.elf
2. Program the bitstream:
openFPGALoader -b vcu118 microwatt-litex-vcu118-dram-2026-02-25.bit
Check to see is serial/console is up:
litex_term /dev/ttyUSB2
You should see either DRAM initialization or the litex bios depending upon how quickly you connect to the console after flashing:
+==========================================+
| P O W E R C O M M O N S |
| Microwatt PPC64LE | LiteX SoC |
+==========================================+
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2025 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Feb 25 2026 02:02:36
BIOS CRC passed (9ccc6cfa)
LiteX git sha1: 69f48eb98
--=============== SoC ==================--
CPU: Microwatt @ 125MHz
BUS: wishbone 32-bit @ 4GiB
CSR: 32-bit data little ordering
ROM: 128.0KiB
SRAM: 8.0KiB
L2: 8.0KiB
SDRAM: 2.0GiB 64-bit @ 1000MT/s (CL-9 CWL-9)
MAIN-RAM: 1.0GiB
--========== Initialization ============--
Initializing SDRAM @0x00000000...
Switching SDRAM to software control.
Write leveling:
tCK equivalent taps: 592
Cmd/Clk scan (0-296)
|10000 |10000 |11000 |11110| best: 0
Setting Cmd/Clk delay to 0 taps.
Data scan:
m0: |00000000000001111111111| delay: 195
m1: |00000000000111111111111| delay: 162
m2: |00000000000000000111111| delay: 262
m3: |00000000000000000001111| delay: 293
m4: |10000000000000000000111| delay: 307
m5: |00000000000000000001111| delay: 295
m6: |10000000000000000001111| delay: 304
m7: |11000000000000000000011| delay: 326
Write latency calibration:
m0:0 m1:0 m2:0 m3:0 m4:0 m5:0 m6:0 m7:0
Read leveling:
m0, b00: |00000000000000000000000000000000| delays: -
m0, b01: |11100000000000000000000000000000| delays: 18+-18
m0, b02: |00000000111111111111110000000000| delays: 226+-114
m0, b03: |00000000000000000000000000111111| delays: 461+-50
m0, b04: |00000000000000000000000000000000| delays: -
m0, b05: |00000000000000000000000000000000| delays: -
m0, b06: |00000000000000000000000000000000| delays: -
m0, b07: |00000000000000000000000000000000| delays: -
best: m0, b02 delays: 225+-113
m1, b00: |00000000000000000000000000000000| delays: -
m1, b01: |11100000000000000000000000000000| delays: 19+-19
m1, b02: |00000000111111111111000000000000| delays: 218+-105
m1, b03: |00000000000000000000000000111111| delays: 458+-52
m1, b04: |00000000000000000000000000000000| delays: -
m1, b05: |00000000000000000000000000000000| delays: -
m1, b06: |00000000000000000000000000000000| delays: -
m1, b07: |00000000000000000000000000000000| delays: -
best: m1, b02 delays: 218+-105
m2, b00: |00000000000000000000000000000000| delays: -
m2, b01: |00000000000000000000000000000000| delays: -
m2, b02: |00011111111111111000000000000000| delays: 155+-112
m2, b03: |00000000000000000000011111111111| delays: 423+-88
m2, b04: |00000000000000000000000000000000| delays: -
m2, b05: |00000000000000000000000000000000| delays: -
m2, b06: |00000000000000000000000000000000| delays: -
m2, b07: |00000000000000000000000000000000| delays: -
best: m2, b02 delays: 154+-112
m3, b00: |00000000000000000000000000000000| delays: -
m3, b01: |00000000000000000000000000000000| delays: -
m3, b02: |00000111111111111110000000000000| delays: 176+-112
m3, b03: |00000000000000000000000111111111| delays: 434+-76
m3, b04: |00000000000000000000000000000000| delays: -
m3, b05: |00000000000000000000000000000000| delays: -
m3, b06: |00000000000000000000000000000000| delays: -
m3, b07: |00000000000000000000000000000000| delays: -
best: m3, b02 delays: 177+-114
m4, b00: |00000000000000000000000000000000| delays: -
m4, b01: |00000000000000000000000000000000| delays: -
m4, b02: |11111111111100000000000000000000| delays: 92+-92
m4, b03: |00000000000000001111111111111100| delays: 361+-110
m4, b04: |00000000000000000000000000000000| delays: -
m4, b05: |00000000000000000000000000000000| delays: -
m4, b06: |00000000000000000000000000000000| delays: -
m4, b07: |00000000000000000000000000000000| delays: -
best: m4, b03 delays: 363+-111
m5, b00: |00000000000000000000000000000000| delays: -
m5, b01: |00000000000000000000000000000000| delays: -
m5, b02: |11111111100000000000000000000000| delays: 68+-68
m5, b03: |00000000000000111111111111100000| delays: 322+-102
m5, b04: |00000000000000000000000000000000| delays: 509+-02
m5, b05: |00000000000000000000000000000000| delays: -
m5, b06: |00000000000000000000000000000000| delays: -
m5, b07: |00000000000000000000000000000000| delays: -
best: m5, b03 delays: 319+-103
m6, b00: |00000000000000000000000000000000| delays: -
m6, b01: |00000000000000000000000000000000| delays: -
m6, b02: |11111111111111000000000000000000| delays: 110+-110
m6, b03: |00000000000000000001111111111111| delays: 398+-107
m6, b04: |00000000000000000000000000000000| delays: -
m6, b05: |00000000000000000000000000000000| delays: -
m6, b06: |00000000000000000000000000000000| delays: -
m6, b07: |00000000000000000000000000000000| delays: -
best: m6, b02 delays: 108+-108
m7, b00: |00000000000000000000000000000000| delays: -
m7, b01: |00000000000000000000000000000000| delays: -
m7, b02: |00111111111111000000000000000000| delays: 123+-101
m7, b03: |00000000000000000000111111111111| delays: 413+-97
m7, b04: |00000000000000000000000000000000| delays: -
m7, b05: |00000000000000000000000000000000| delays: -
m7, b06: |00000000000000000000000000000000| delays: -
m7, b07: |00000000000000000000000000000000| delays: -
best: m7, b02 delays: 124+-103
Switching SDRAM to hardware control.
Memtest at 0 (2.0MiB)...
Write: 0x0-0x200000 2.0MiB
Read: 0x0-0x200000 2.0MiB
Memtest OK
Memspeed at 0 (Sequential, 2.0MiB)...
Write speed: 117.2MiB/s
Read speed: 151.8MiB/s
Setting up exception vectors... done.
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
Press ctrl-c twice to exit.
3. Load Linux
litex_term --kernel linux-6.12.0-2026-litex-02-25.dtbImage.microwatt.elf --kernel-adr 0x5000000 --serial-boot /dev/ttyUSB2
Replace /dev/ttyUSB2 wit your USB console output. Press enter two times after the command and you will see a litex console. Type serialbootand press enter. Your screen should like below with login shell at the end:
litex> serialboot
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
[LITEX-TERM] Received firmware download request from the device.
[LITEX-TERM] Uploading /home/powercommons/bitstreams/linux-6.12.0-litex-2026-02-25.dtbImage.microwatt.elf to 0x05000000 (5082344 bytes)...
[LITEX-TERM] Upload calibration... (inter-frame: 10.00us, length: 64)
[LITEX-TERM] Upload complete (9.9KB/s).
[LITEX-TERM] Booting the device.
[LITEX-TERM] Done.
ELF: Valid PPC64LE binary, entry=0x01300000
ELF: Loading segment 0: 0x004c6400 bytes to 0x1300000
Executing booted program at 0x01300000
--============= Liftoff! ===============--
[ 0.000000] dt-cpu-ftrs: setup for ISA 3000
[ 0.000000] dt-cpu-ftrs: final cpu/mmu features = 0x0000008380039181 0x20005040
[ 0.000000] radix-mmu: Page sizes from device-tree:
[ 0.000000] radix-mmu: Page size shift = 12 AP=0x0
[ 0.000000] radix-mmu: Page size shift = 16 AP=0x5
[ 0.000000] radix-mmu: Page size shift = 21 AP=0x1
[ 0.000000] radix-mmu: Page size shift = 30 AP=0x2
[ 0.000000] radix-mmu: Mapped 0x0000000000000000-0x0000000001400000 with 2.00 MiB pages (exec)
[ 0.000000] radix-mmu: Mapped 0x0000000001400000-0x0000000020000000 with 2.00 MiB pages
[ 0.000000] radix-mmu: Initializing Radix MMU
[ 0.000000] Linux version 6.12.0 (powercommons@DESKTOP-ECRAP4O) (powerpc64le-buildroot-linux-gnu-gcc.br_real (Buildroot 2025.02.10-51-g4df2c68d0f-dirty) 13.4.0, GNU ld (GNU Binutils) 2.43.1) #2 Wed Feb 25 02:12:35 EET 2026
[ 0.000000] Hardware name: Microwatt 0x630000 microwatt
[ 0.000000] -----------------------------------------------------
[ 0.000000] phys_mem_size = 0x20000000
[ 0.000000] dcache_bsize = 0x40
[ 0.000000] icache_bsize = 0x40
[ 0.000000] cpu_features = 0x0000008380039181
[ 0.000000] possible = 0x001ffbebcb5fb185
[ 0.000000] always = 0x0000000380008181
[ 0.000000] cpu_user_features = 0xcc002102 0x88800000
[ 0.000000] mmu_features = 0x20005040
[ 0.000000] firmware_features = 0x0000000000000000
[ 0.000000] vmalloc start = 0xc008000000000000
[ 0.000000] IO start = 0xc00a000000000000
[ 0.000000] vmemmap start = 0xc00c000000000000
[ 0.000000] -----------------------------------------------------
[ 0.000000] barrier-nospec: using ORI speculation barrier
[ 0.000000] Zone ranges:
[ 0.000000] Normal [mem 0x0000000000000000-0x000000001fffffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000000000000-0x000000001fffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x000000001fffffff]
[ 0.000000] Kernel command line:
[ 0.000000] Dentry cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
[ 0.000000] Inode-cache hash table entries: 32768 (order: 6, 262144 bytes, linear)
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 131072
[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
[ 0.000000] SLUB: HWalign=128, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 16
[ 0.000000] ICS native initialized for sources 16..31
[ 0.000000] ICS native backend registered
[ 0.000144] time_init: 64 bit decrementer (max: 7fffffffffffffff)
[ 0.000292] clocksource: timebase: mask: 0xffffffffffffffff max_cycles: 0x39a85c4118, max_idle_ns: 881590405314 ns
[ 0.000479] clocksource: timebase mult[4000000] shift[23] registered
[ 0.002451] pid_max: default: 32768 minimum: 301
[ 0.004559] Mount-cache hash table entries: 1024 (order: 1, 8192 bytes, linear)
[ 0.004889] Mountpoint-cache hash table entries: 1024 (order: 1, 8192 bytes, linear)
[ 0.042938] Memory: 474044K/524288K available (4364K kernel code, 460K rwdata, 12020K rodata, 2220K init, 306K bss, 49052K reserved, 0K cma-reserved)
[ 0.047762] devtmpfs: initialized
[ 0.095252] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[ 0.095558] futex hash table entries: 256 (order: 0, 6144 bytes, linear)
[ 0.116811] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[ 0.143887] platform soc@c0000000: Fixed dependency cycle(s) with /soc@c0000000/interrupt-controller@bff1000
[ 0.150267] platform soc@c0000000: Fixed dependency cycle(s) with /soc@c0000000/interrupt-controller@bff1000
[ 0.197569] pps_core: LinuxPPS API ver. 1 registered
[ 0.197695] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <[email protected]>
[ 0.198289] PTP clock support registered
[ 0.216145] clocksource: Switched to clocksource timebase
[ 0.245834] NET: Registered PF_INET protocol family
[ 0.249281] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
[ 0.263361] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
[ 0.263712] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
[ 0.264177] TCP established hash table entries: 4096 (order: 3, 32768 bytes, linear)
[ 0.264911] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
[ 0.267771] TCP: Hash tables configured (established 4096 bind 4096)
[ 0.269531] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
[ 0.269895] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
[ 0.272103] NET: Registered PF_UNIX/PF_LOCAL protocol family
[ 0.298495] workingset: timestamp_bits=62 max_order=17 bucket_order=0
[ 0.316858] io scheduler mq-deadline registered
[ 0.317280] io scheduler bfq registered
[ 0.348307] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 0.411624] c8003800.serial: ttyLXU0 at MMIO 0x0 (irq = 16, base_baud = 0) is a liteuart
[ 0.412114] printk: legacy console [liteuart0] enabled
[ 1.745740] brd: module loaded
[ 1.981850] loop: module loaded
[ 2.010726] NET: Registered PF_INET6 protocol family
[ 2.068458] Segment Routing with IPv6
[ 2.072120] In-situ OAM (IOAM) with IPv6
[ 2.076406] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[ 2.121932] NET: Registered PF_PACKET protocol family
[ 2.682557] clk: Disabling unused clocks
[ 3.877907] Freeing unused kernel image (initmem) memory: 2220K
[ 3.893489] Run /init as init process
Saving 256 bits of non-creditable seed for next boot
Starting syslogd: OK
Starting klogd: OK
Running sysctl: OK
Starting network: OK
Starting crond: OK
+==========================================+
| P O W E R C O M M O N S |
| Microwatt PPC64LE | LiteX SoC |
| Xilinx VCU-118 |
| [email protected] |
+==========================================+
vcu118-litex-microwatt login:
See Release for other images.
Next Steps
No FPGA Hardware?
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